feat(IMSIC): modify the addrmap between ree and tee (#37)

* feat(IMSIC): modify the addrmap between ree and tee

* feat(IMSIC): modify addrmap between tee and ree

* feat(IMSIC): modify addrmap between tee and ree

Author: zhaohong1988

src/main/scala/IMSIC.scala

@@ -147,9 +147,10 @@ case class IMSICParams(
 
   lazy val eixNum: Int = pow2(imsicIntSrcWidth).toInt / xlen // number of eip/eie registers
   lazy val intFileMemWidth: Int = 12 // interrupt file memory region width: 12-bit width => 4KB size
-  lazy val tee_shift: Int = 1 + HartIDBits + log2Ceil(1+ geilen) + intFileMemWidth // 9: max 512 hart, bit10 is 1, tee imsic accessed.
-  lazy val tee_mAddr: Long = mAddr | (1L << tee_shift)
-  lazy val tee_sgAddr: Long = sgAddr | (1L << tee_shift)
+  lazy val tee_mshift: Int = HartIDBits + intFileMemWidth // 9: max 512 hart, bit10 is 1, tee imsic accessed.
+  lazy val tee_sshift: Int = HartIDBits + log2Ceil(1+ geilen) + intFileMemWidth // 9: max 512 hart, bit10 is 1, tee imsic accessed.
+  lazy val tee_mAddr: Long = mAddr + (1L << tee_mshift)
+  lazy val tee_sgAddr: Long = sgAddr + (1L << tee_sshift)
   require(vgeinWidth >= log2Ceil(geilen))
   require(
     iselectWidth >= 8,