cpu: remove legacy resolve update path

Yakkhini · Yakkhini · commit 2e46566d0b39 · 2026-04-08T16:36:53.000+08:00
Collapse resolved-stage BTB training onto the packet-based full resolve path, remove the old resolvedCFI/resolveQueue helper chain, and reinterpret config intent around full-resolve participation versus commit fallback.

Change-Id: I777f46178bc7b1ce891bb2242cefff0b166e48a2
diff --git a/configs/example/idealkmhv3.py b/configs/example/idealkmhv3.py
@@ -83,6 +83,7 @@ def setKmhV3IdealParams(args, system):
 
         # branch predictor
         if args.bp_type == 'DecoupledBPUWithBTB':
+            cpu.enableFullResolveTrain = False
             cpu.branchPred.ftq_size = 64
             cpu.branchPred.fsq_size = 64
             # cpu.branchPred.microtage.enabled = False
diff --git a/configs/example/kmhv3.py b/configs/example/kmhv3.py
@@ -93,17 +93,14 @@ def setKmhV3Params(args, system):
 
         # branch predictor
         if args.bp_type == 'DecoupledBPUWithBTB':
+            cpu.enableFullResolveTrain = True
             cpu.branchPred.ftq_size = 64
             cpu.branchPred.fsq_size = 64
 
             if args.btb_tage_upper_bound:
                 cpu.branchPred.tage = BTBTAGEUpperBound(
                     usePathHashHistory=True)
 
-            cpu.branchPred.mbtb.resolvedUpdate = True
-            cpu.branchPred.tage.resolvedUpdate = True
-            cpu.branchPred.ittage.resolvedUpdate = True
-
             cpu.branchPred.ubtb.enabled = True
             cpu.branchPred.abtb.enabled = True
             cpu.branchPred.microtage.enabled = True
diff --git a/src/cpu/o3/BaseO3CPU.py b/src/cpu/o3/BaseO3CPU.py
@@ -248,9 +248,7 @@ def support_take_over(cls):
                                        "Branch Predictor")
     resolveQueueSize = Param.Unsigned(16, "Number of entries in the branch resolution queue")
     enableFullResolveTrain = Param.Bool(True,
-        "Enable packet-based resolve training rollout plumbing")
-    enableLegacyResolveUpdate = Param.Bool(True,
-        "Enable legacy PC-only resolve update")
+        "Train eligible BTB components from full resolve packets instead of commit fallback")
     needsTSO = Param.Bool(False, "Enable TSO Memory model")
 
     scheduler = Param.Scheduler("")
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
@@ -197,12 +197,6 @@ struct SquashVersion
     SquashVersion() : version(0) {}
 };
 
-struct ResolveQueueEntry
-{
-    uint64_t resolvedFTQId;
-    std::vector<uint64_t> resolvedInstPC;
-};
-
 /** Struct that defines all backwards communication. */
 struct TimeStruct
 {
@@ -239,14 +233,6 @@ struct TimeStruct
         StallReason lqHeadStallReason;
         StallReason sqHeadStallReason;
 
-        struct ResolvedCFIEntry
-        {
-            uint64_t ftqId;
-            uint64_t pc;
-        };
-        /** Resolved control-flow PCs produced this cycle (fetch buffers/merges). */
-        std::vector<ResolvedCFIEntry> resolvedCFIs;  // *F
-
         struct ResolveTrainEntry
         {
             uint64_t ftqId;
diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
@@ -115,7 +115,6 @@ Fetch::Fetch(CPU *_cpu, const BaseO3CPUParams &params)
       branchPred(nullptr),
       resolveQueueSize(params.resolveQueueSize),
       enableFullResolveTrain(params.enableFullResolveTrain),
-      enableLegacyResolveUpdate(params.enableLegacyResolveUpdate),
       decodeToFetchDelay(params.decodeToFetchDelay),
       renameToFetchDelay(params.renameToFetchDelay),
       iewToFetchDelay(params.iewToFetchDelay),
@@ -285,16 +284,6 @@ Fetch::FetchStatGroup::FetchStatGroup(CPU *cpu, Fetch *fetch)
                     statistics::units::Count, statistics::units::Cycle>::get(),
              "Frontend Bandwidth Bound",
              frontendBound - frontendLatencyBound),
-    ADD_STAT(resolveQueueFullEvents, statistics::units::Count::get(),
-             "Number of events the resolve queue becomes full"),
-    ADD_STAT(resolveEnqueueFailEvent, statistics::units::Count::get(),
-             "Number of times an entry could not be enqueued to the resolve queue"),
-    ADD_STAT(resolveDequeueCount, statistics::units::Count::get(),
-             "Number of times an entry is dequeued from the resolve queue"),
-    ADD_STAT(resolveEnqueueCount, statistics::units::Count::get(),
-             "Number of times an entry is enqueued to the resolve queue"),
-    ADD_STAT(resolveQueueOccupancy, statistics::units::Count::get(),
-             "Number of entries in the resolve queue"),
     ADD_STAT(fullResolveEntriesReceived, statistics::units::Count::get(),
              "Number of full resolve entries received by fetch"),
     ADD_STAT(fullResolveEntriesMerged, statistics::units::Count::get(),
@@ -387,10 +376,6 @@ Fetch::FetchStatGroup::FetchStatGroup(CPU *cpu, Fetch *fetch)
             .flags(statistics::total);
         frontendBandwidthBound
             .flags(statistics::total);
-        resolveEnqueueCount
-            .init(1, 8, 1);
-        resolveQueueOccupancy
-            .init(0, 32, 1);
         fullResolveEntriesReceived
             .prereq(fullResolveEntriesReceived);
         fullResolveEntriesMerged
@@ -1517,70 +1502,6 @@ Fetch::handleIEWSignals()
         return;
     }
 
-    auto &incoming = fromIEW->iewInfo->resolvedCFIs;
-
-    if (!enableLegacyResolveUpdate) {
-        for (ThreadID tid = 0; tid < numThreads; ++tid) {
-            fromIEW->iewInfo[tid].resolvedCFIs.clear();
-        }
-    }
-
-    if (enableLegacyResolveUpdate) {
-        const bool had_pending_resolve = !resolveQueue.empty();
-        uint8_t enqueueSize = fromIEW->iewInfo->resolvedCFIs.size();
-        uint8_t enqueueCount = 0;
-
-        if (resolveQueueSize && resolveQueue.size() > resolveQueueSize - 4) {
-            fetchStats.resolveQueueFullEvents++;
-            fetchStats.resolveEnqueueFailEvent += enqueueSize;
-        } else {
-
-            for (const auto &resolved : incoming) {
-                bool merged = false;
-                for (auto &queued : resolveQueue) {
-                    if (queued.resolvedFTQId == resolved.ftqId) {
-                        queued.resolvedInstPC.push_back(resolved.pc);
-                        merged = true;
-                        break;
-                    }
-                }
-
-                if (merged) {
-                    continue;
-                }
-
-                ResolveQueueEntry new_entry;
-                new_entry.resolvedFTQId = resolved.ftqId;
-                new_entry.resolvedInstPC.push_back(resolved.pc);
-                resolveQueue.push_back(std::move(new_entry));
-                enqueueCount++;
-            }
-            fetchStats.resolveEnqueueCount.sample(enqueueCount);
-        }
-
-        fetchStats.resolveQueueOccupancy.sample(resolveQueue.size());
-
-        // Process only entries that were already pending before this cycle.
-        // This preserves a cycle of separation between IEW producing resolved
-        // CFIs and fetch consuming them as predictor resolved updates.
-        if (had_pending_resolve && !resolveQueue.empty()) {
-            auto &entry = resolveQueue.front();
-            unsigned int stream_id = entry.resolvedFTQId;
-            dbpbtb->prepareResolveUpdateEntries(stream_id, 0);
-            for (const auto resolvedInstPC : entry.resolvedInstPC) {
-                dbpbtb->markCFIResolved(stream_id, resolvedInstPC, 0);
-            }
-            bool success = dbpbtb->resolveUpdate(stream_id, 0);
-            if (success) {
-                dbpbtb->notifyResolveSuccess();
-                resolveQueue.pop_front();
-                fetchStats.resolveDequeueCount++;
-            } else {
-                dbpbtb->notifyResolveFailure();
-            }
-        }
-    }
-
     if (!enableFullResolveTrain) {
         for (ThreadID tid = 0; tid < numThreads; ++tid) {
             fromIEW->iewInfo[tid].resolveTrainEntries.clear();
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
@@ -465,8 +465,7 @@ class Fetch
      */
     bool handleCommitSignals(ThreadID tid);
 
-    /** Handles iew signals including resolved cfi, mark their btb entries
-     *  and train predictors if they are configured to update in resolve stage.
+    /** Handles IEW signals for full resolve-train predictor updates.
      */
     void handleIEWSignals();
 
@@ -639,12 +638,6 @@ class Fetch
     /** Enable packet-based resolve training rollout plumbing. */
     const bool enableFullResolveTrain;
 
-    /** Keep legacy PC-only resolve updates enabled. */
-    const bool enableLegacyResolveUpdate;
-
-    /** FIFO storing resolve entries waiting for BPU training. */
-    std::deque<ResolveQueueEntry> resolveQueue;
-
     /** FIFO storing aggregated full resolve-train entries. */
     std::deque<ResolveTrainQueueEntry> resolveTrainQueue;
 
@@ -1129,17 +1122,6 @@ class Fetch
         statistics::Formula frontendLatencyBound;
         /** Frontend Bandwidth Bound */
         statistics::Formula frontendBandwidthBound;
-        /** Stat for total cycles the resolve queue is full. */
-        statistics::Scalar resolveQueueFullEvents;
-        /** Stat for total number of resolve enqueue fail events. */
-        statistics::Scalar resolveEnqueueFailEvent;
-
-        /** Stat for total number of resolve dequeue events. */
-        statistics::Scalar resolveDequeueCount;
-        /** Stat for total number of resolve enqueue events. */
-        statistics::Distribution resolveEnqueueCount;
-        /** Stat for entry occupancy distribution of the resolve queue. */
-        statistics::Distribution resolveQueueOccupancy;
         /** Full resolve entries observed at fetch. */
         statistics::Scalar fullResolveEntriesReceived;
         /** Full resolve entries merged with an existing target. */
diff --git a/src/cpu/o3/iew.cc b/src/cpu/o3/iew.cc
@@ -1442,14 +1442,6 @@ IEW::SquashCheckAfterExe(DynInstPtr inst)
             is_control && !loadNotExecuted && inst->mispredicted();
 
         if (is_control) {
-            if (params.enableLegacyResolveUpdate) {
-                auto &resolved_cfis = toFetch->iewInfo[tid].resolvedCFIs;
-                TimeStruct::IewComm::ResolvedCFIEntry entry;
-                entry.ftqId = inst->getFtqId();
-                entry.pc = inst->getPC();
-                resolved_cfis.push_back(entry);
-            }
-
             if (params.enableFullResolveTrain) {
                 auto &resolve_entries = toFetch->iewInfo[tid].resolveTrainEntries;
                 TimeStruct::IewComm::ResolveTrainEntry entry;
@@ -1556,10 +1548,10 @@ IEW::executeInsts()
     // @todo This doesn't actually work anymore, we should fix it.
 //    printAvailableInsts();
 
-    // Clear resolvedFSQId and resolvedInstPC since they are already handled in frontend
-    ThreadID tid = *activeThreads->begin();
-    toFetch->iewInfo[tid].resolvedCFIs.clear();
-    toFetch->iewInfo[tid].resolveTrainEntries.clear();
+    // Clear resolve-train entries before producing this cycle's updates.
+    for (ThreadID active_tid : *activeThreads) {
+        toFetch->iewInfo[active_tid].resolveTrainEntries.clear();
+    }
 
     // Execute/writeback any instructions that are available.
     int insts_to_execute = fromIssue->size;
diff --git a/src/cpu/pred/BranchPredictor.py b/src/cpu/pred/BranchPredictor.py
@@ -968,7 +968,8 @@ class TimedBaseBTBPredictor(SimObject):
     blockSize = Param.Unsigned(Parent.predictWidth, "Block size in bytes")
     predictWidth = Param.Unsigned(Parent.predictWidth, "Maximum range in bytes that a single prediction can cover")
     numDelay = Param.Unsigned(1000, "Number of bubbles to put on a prediction")
-    resolvedUpdate = Param.Bool(False, "Enable resolved update, no need to wait until commit")
+    resolvedUpdate = Param.Bool(False,
+        "Train from full resolve packets instead of commit fallback")
     enabled = Param.Bool(True, "Enable this predictor component")
 
 class MBTB(TimedBaseBTBPredictor):
@@ -982,6 +983,8 @@ class MBTB(TimedBaseBTBPredictor):
     numThreads = Param.Unsigned(1, "Number of threads")
     numWays = Param.Unsigned(4, "Number of ways per set") # for 2 SRAMs, 4 ways per SRAM
     numDelay = 2
+    resolvedUpdate = Param.Bool(Parent.enableFullResolveTrain,
+        "Train MBTB from full resolve packets instead of commit fallback")
     blockSize = 32  # max 64 byte block, 32 byte aligned
     # MBTB is always half-aligned - no parameter needed
     victimCacheSize = Param.Unsigned(0, "Number of entries in the victim cache")
@@ -1059,6 +1062,8 @@ class BTBTAGE(TimedBaseBTBPredictor):
     numBanks = Param.Unsigned(4, "Number of banks for bank conflict simulation")
     enableBankConflict = Param.Bool(False, "Enable bank conflict simulation")
     numDelay = 2
+    resolvedUpdate = Param.Bool(Parent.enableFullResolveTrain,
+        "Train BTBTAGE from full resolve packets instead of commit fallback")
 
 class BTBTAGEUpperBound(BTBTAGE):
     type = 'BTBTAGEUpperBound'
@@ -1114,6 +1119,8 @@ class BTBITTAGE(TimedBaseBTBPredictor):
     maxHistLen = Param.Unsigned(970, "The length of history passed from DBP")
     numTablesToAlloc = Param.Unsigned(1,"The number of table to allocated each time")
     numDelay = 2
+    resolvedUpdate = Param.Bool(Parent.enableFullResolveTrain,
+        "Train BTBITTAGE from full resolve packets instead of commit fallback")
 
 class BTBMGSC(TimedBaseBTBPredictor):
     type = 'BTBMGSC'
@@ -1207,6 +1214,4 @@ class DecoupledBPUWithBTB(BranchPredictor):
     bpDBSwitches = VectorParam.String([], "Enable which traces in the form of database")
     resolveBlockThreshold = Param.Unsigned(8, "Consecutive resolve dequeue failures before blocking prediction once")
     enableFullResolveTrain = Param.Bool(Parent.enableFullResolveTrain,
-        "Enable packet-based resolve training rollout plumbing")
-    enableLegacyResolveUpdate = Param.Bool(Parent.enableLegacyResolveUpdate,
-        "Enable legacy PC-only resolve update")
+        "Train eligible BTB components from full resolve packets instead of commit fallback")
diff --git a/src/cpu/pred/btb/btb_ittage.cc b/src/cpu/pred/btb/btb_ittage.cc
@@ -223,17 +223,12 @@ BTBITTAGE::update(const FetchTarget &stream)
         all_entries_to_update.push_back(stream.updateNewBTBEntry);
     }
 
-    // // only update indirect branches that are not returns
-    if (getResolvedUpdate()) {
-        auto remove_it =
-            std::remove_if(all_entries_to_update.begin(), all_entries_to_update.end(),
-                           [](const BTBEntry &e) { return !(e.isIndirect && !e.isReturn && e.resolved); });
-        all_entries_to_update.erase(remove_it, all_entries_to_update.end());
-    } else {
-        auto remove_it = std::remove_if(all_entries_to_update.begin(), all_entries_to_update.end(),
-                                        [](const BTBEntry &e) { return !(e.isIndirect && !e.isReturn); });
-        all_entries_to_update.erase(remove_it, all_entries_to_update.end());
-    }
+    auto remove_it = std::remove_if(all_entries_to_update.begin(),
+                                    all_entries_to_update.end(),
+                                    [](const BTBEntry &e) {
+                                        return !(e.isIndirect && !e.isReturn);
+                                    });
+    all_entries_to_update.erase(remove_it, all_entries_to_update.end());
 
     // get tage predictions from meta
     // TODO: use component idx
diff --git a/src/cpu/pred/btb/btb_tage.cc b/src/cpu/pred/btb/btb_tage.cc
@@ -423,16 +423,9 @@ BTBTAGE::prepareUpdateEntries(const FetchTarget &stream) {
         all_entries.push_back(potential_new_entry);
     }
 
-    // Filter: only keep conditional branches that are not always taken
-    if (getResolvedUpdate()) {
-        auto remove_it = std::remove_if(all_entries.begin(), all_entries.end(),
-            [](const BTBEntry &e) { return !(e.isCond && !e.alwaysTaken && e.resolved); });
-        all_entries.erase(remove_it, all_entries.end());
-    } else {
-        auto remove_it = std::remove_if(all_entries.begin(), all_entries.end(),
-            [](const BTBEntry &e) { return !(e.isCond && !e.alwaysTaken); });
-        all_entries.erase(remove_it, all_entries.end());
-    }
+    auto remove_it = std::remove_if(all_entries.begin(), all_entries.end(),
+        [](const BTBEntry &e) { return !(e.isCond && !e.alwaysTaken); });
+    all_entries.erase(remove_it, all_entries.end());
 
     return all_entries;
 }
diff --git a/src/cpu/pred/btb/decoupled_bpred.cc b/src/cpu/pred/btb/decoupled_bpred.cc
diff --git a/src/cpu/pred/btb/decoupled_bpred.hh b/src/cpu/pred/btb/decoupled_bpred.hh
diff --git a/src/cpu/pred/btb/mbtb.cc b/src/cpu/pred/btb/mbtb.cc
