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YakkhiniYakkhini
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cpu: do not save metas another time
Change-Id: I736783b6b3bb469c7a02d060e9317ee24879d31a
1 parent a835592 commit 66148cb

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11 files changed

+40
-62
lines changed

11 files changed

+40
-62
lines changed

‎src/cpu/o3/fetch.cc‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -87,19 +87,6 @@ namespace
8787
constexpr uint8_t RvcInstBytes = 2;
8888
constexpr uint8_t BaseInstBytes = 4;
8989

90-
size_t
91-
resolveTrainMetaCount(
92-
const branch_prediction::btb_pred::FetchTarget &target)
93-
{
94-
size_t num_pred_metas = 0;
95-
for (size_t i = 0; i < target.predMetas.size(); ++i) {
96-
if (target.predMetas[i] != nullptr) {
97-
num_pred_metas = i + 1;
98-
}
99-
}
100-
return num_pred_metas;
101-
}
102-
10390
} // anonymous namespace
10491

10592
Fetch::IcachePort::IcachePort(Fetch *_fetch, CPU *_cpu) :
@@ -1686,8 +1673,6 @@ Fetch::buildResolvedTrainPacket(const ResolveTrainQueueEntry &entry) const
16861673
packet.tid = entry.tid;
16871674
packet.target = {entry.ftqId, entry.generation};
16881675
packet.startPC = target.startPC;
1689-
packet.numPredMetas = resolveTrainMetaCount(target);
1690-
packet.predMetas = target.predMetas;
16911676
packet.realBranches.reserve(entry.insts.size());
16921677

16931678
for (const auto &inst_data : entry.insts) {

‎src/cpu/o3/fetch.hh‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1152,7 +1152,6 @@ class Fetch
11521152
statistics::Scalar fullResolveEntriesDroppedGenerationMismatch;
11531153
/** Full resolve packets sent to the predictor. */
11541154
statistics::Scalar fullResolvePacketsSent;
1155-
11561155
// Trace metadata accounting (trace mode)
11571156
/** Number of stored trace metadata records (seqNum -> traceInst). */
11581157
statistics::Scalar traceMetaStores;

‎src/cpu/pred/btb/btb_ittage.cc‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -391,18 +391,20 @@ BTBITTAGE::update(const FetchTarget &stream)
391391
}
392392

393393
bool
394-
BTBITTAGE::canResolveTrain(const ResolvedTrainPacket &packet)
394+
BTBITTAGE::canResolveTrain(const ResolvedTrainPacket &packet,
395+
const FetchTarget &target)
395396
{
396397
return true;
397398
}
398399

399400
void
400-
BTBITTAGE::resolveTrain(const ResolvedTrainPacket &packet)
401+
BTBITTAGE::resolveTrain(const ResolvedTrainPacket &packet,
402+
const FetchTarget &target)
401403
{
402404
auto predMeta = std::static_pointer_cast<TageMeta>(
403-
packet.predMetas[getComponentIdx()]);
405+
target.predMetas[getComponentIdx()]);
404406
if (!predMeta) {
405-
DPRINTF(ITTAGE, "resolveTrain: no prediction meta, skip\n");
407+
DPRINTF(ITTAGE, "resolveTrain: no live prediction meta, skip\n");
406408
return;
407409
}
408410

‎src/cpu/pred/btb/btb_ittage.hh‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -111,8 +111,10 @@ class BTBITTAGE : public TimedBaseBTBPredictor
111111
const FetchTarget &entry,int shamt, bool cond_taken) override;
112112

113113
void update(const FetchTarget &entry) override;
114-
bool canResolveTrain(const ResolvedTrainPacket &packet) override;
115-
void resolveTrain(const ResolvedTrainPacket &packet) override;
114+
bool canResolveTrain(const ResolvedTrainPacket &packet,
115+
const FetchTarget &target) override;
116+
void resolveTrain(const ResolvedTrainPacket &packet,
117+
const FetchTarget &target) override;
116118

117119
void commitBranch(const FetchTarget &stream, const DynInstPtr &inst) override;
118120

‎src/cpu/pred/btb/btb_tage.cc‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -680,7 +680,8 @@ BTBTAGE::canResolveUpdate(const FetchTarget &stream) {
680680
}
681681

682682
bool
683-
BTBTAGE::canResolveTrain(const ResolvedTrainPacket &packet)
683+
BTBTAGE::canResolveTrain(const ResolvedTrainPacket &packet,
684+
const FetchTarget &target)
684685
{
685686
Addr startAddr = packet.startPC;
686687
unsigned updateBank = getBankId(startAddr);
@@ -749,16 +750,17 @@ BTBTAGE::prepareResolveTrainEntries(const ResolvedTrainPacket &packet,
749750
}
750751

751752
void
752-
BTBTAGE::resolveTrain(const ResolvedTrainPacket &packet)
753+
BTBTAGE::resolveTrain(const ResolvedTrainPacket &packet,
754+
const FetchTarget &target)
753755
{
754756
if (enableBankConflict && predBankValid) {
755757
predBankValid = false;
756758
}
757759

758760
auto predMeta = std::static_pointer_cast<TageMeta>(
759-
packet.predMetas[getComponentIdx()]);
761+
target.predMetas[getComponentIdx()]);
760762
if (!predMeta) {
761-
DPRINTF(TAGE, "resolveTrain: no prediction meta, skip\n");
763+
DPRINTF(TAGE, "resolveTrain: no live prediction meta, skip\n");
762764
return;
763765
}
764766

‎src/cpu/pred/btb/btb_tage.hh‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -161,8 +161,10 @@ class BTBTAGE : public TimedBaseBTBPredictor
161161
void update(const FetchTarget &entry) override;
162162
bool canResolveUpdate(const FetchTarget &entry) override;
163163
void doResolveUpdate(const FetchTarget &entry) override;
164-
bool canResolveTrain(const ResolvedTrainPacket &packet) override;
165-
void resolveTrain(const ResolvedTrainPacket &packet) override;
164+
bool canResolveTrain(const ResolvedTrainPacket &packet,
165+
const FetchTarget &target) override;
166+
void resolveTrain(const ResolvedTrainPacket &packet,
167+
const FetchTarget &target) override;
166168

167169
#ifndef UNIT_TEST
168170
void commitBranch(const FetchTarget &stream, const DynInstPtr &inst) override;

‎src/cpu/pred/btb/common.hh‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -292,15 +292,11 @@ struct ResolvedTrainPacket
292292
ThreadID tid;
293293
FetchTargetIdentity target;
294294
Addr startPC;
295-
size_t numPredMetas;
296-
std::array<std::shared_ptr<void>, MaxPredictorComponents> predMetas;
297295
std::vector<ResolvedBranch> realBranches;
298296

299297
ResolvedTrainPacket()
300-
: tid(0), target(), startPC(0), numPredMetas(0), predMetas(),
301-
realBranches()
298+
: tid(0), target(), startPC(0), realBranches()
302299
{
303-
predMetas.fill(nullptr);
304300
}
305301
};
306302

‎src/cpu/pred/btb/decoupled_bpred.cc‎

Lines changed: 4 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -25,25 +25,8 @@ namespace
2525
{
2626

2727
bool
28-
validateResolvedTrainPacket(const ResolvedTrainPacket &packet,
29-
const FetchTarget &target,
30-
unsigned numComponents)
28+
validateResolvedTrainPacket(const ResolvedTrainPacket &packet)
3129
{
32-
if (packet.numPredMetas > packet.predMetas.size()) {
33-
return false;
34-
}
35-
36-
if (numComponents > packet.predMetas.size() ||
37-
packet.numPredMetas != numComponents) {
38-
return false;
39-
}
40-
41-
for (unsigned i = 0; i < numComponents; ++i) {
42-
if (packet.predMetas[i] != target.predMetas[i]) {
43-
return false;
44-
}
45-
}
46-
4730
uint8_t lastOffset = 0;
4831
Addr lastPc = 0;
4932
bool firstBranch = true;
@@ -718,7 +701,7 @@ DecoupledBPUWithBTB::resolveTrain(
718701
return false;
719702
}
720703

721-
if (!validateResolvedTrainPacket(packet, target, numComponents)) {
704+
if (!validateResolvedTrainPacket(packet)) {
722705
DPRINTF(DecoupleBP,
723706
"Resolve-train packet validation failed: id=%lu generation=%lu tid=%u\n",
724707
packet.target.id, packet.target.generation, tid);
@@ -731,13 +714,13 @@ DecoupledBPUWithBTB::resolveTrain(
731714
packet.realBranches.size());
732715

733716
for (int i = 0; i < numComponents; ++i) {
734-
if (!components[i]->canResolveTrain(packet)) {
717+
if (!components[i]->canResolveTrain(packet, target)) {
735718
return false;
736719
}
737720
}
738721

739722
for (int i = 0; i < numComponents; ++i) {
740-
components[i]->resolveTrain(packet);
723+
components[i]->resolveTrain(packet, target);
741724
}
742725

743726
return true;

‎src/cpu/pred/btb/mbtb.cc‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -814,17 +814,20 @@ MBTB::update(const FetchTarget &stream)
814814
}
815815

816816
bool
817-
MBTB::canResolveTrain(const ResolvedTrainPacket &packet)
817+
MBTB::canResolveTrain(const ResolvedTrainPacket &packet,
818+
const FetchTarget &target)
818819
{
819-
return getComponentIdx() < packet.numPredMetas;
820+
return true;
820821
}
821822

822823
void
823-
MBTB::resolveTrain(const ResolvedTrainPacket &packet)
824+
MBTB::resolveTrain(const ResolvedTrainPacket &packet,
825+
const FetchTarget &target)
824826
{
825827
auto meta = std::static_pointer_cast<BTBMeta>(
826-
packet.predMetas[getComponentIdx()]);
828+
target.predMetas[getComponentIdx()]);
827829
if (!meta) {
830+
DPRINTF(BTB, "resolveTrain: no live prediction meta, skip\n");
828831
return;
829832
}
830833

‎src/cpu/pred/btb/mbtb.hh‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -171,9 +171,11 @@ class MBTB : public TimedBaseBTBPredictor
171171
*/
172172
void update(const FetchTarget &stream) override;
173173

174-
bool canResolveTrain(const ResolvedTrainPacket &packet) override;
174+
bool canResolveTrain(const ResolvedTrainPacket &packet,
175+
const FetchTarget &target) override;
175176

176-
void resolveTrain(const ResolvedTrainPacket &packet) override;
177+
void resolveTrain(const ResolvedTrainPacket &packet,
178+
const FetchTarget &target) override;
177179

178180
std::vector<BTBEntry> prepareUpdateEntries(const FetchTarget &stream);
179181

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