mem: 8 channel ddr with 100ns delay

edwu186 · edwu186 · commit 7db0e6942fa3 · 2026-01-14T18:24:40.000+08:00
Change-Id: Id9eb322d485fcdab6c918924584a7fdbf5c02a5f
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
@@ -213,7 +213,7 @@ class L3ToMemBus(CoherentXBar):
     # contributions.
     frontend_latency = 0
     forward_latency = 9
-    response_latency = 78
+    response_latency = 191
     snoop_response_latency = 4
 
     # Use a snoop-filter by default
