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Commit a3d686b

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author
Cao Jiaming
committed
cpu-o3: move mbtb to s0
Change-Id: I65f24ad3248d174598d0f09d46757527fc58041d
1 parent 444f903 commit a3d686b

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2 files changed

+4
-4
lines changed

2 files changed

+4
-4
lines changed

src/cpu/pred/BranchPredictor.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -981,7 +981,7 @@ class MBTB(TimedBaseBTBPredictor):
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instShiftAmt = Param.Unsigned(1, "Amount to shift PC to get inst bits")
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numThreads = Param.Unsigned(1, "Number of threads")
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numWays = Param.Unsigned(4, "Number of ways per set") # for 2 SRAMs, 4 ways per SRAM
984-
numDelay = 2
984+
numDelay = 0
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blockSize = 32 # max 64 byte block, 32 byte aligned
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# MBTB is always half-aligned - no parameter needed
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victimCacheSize = Param.Unsigned(0, "Number of entries in the victim cache")

src/cpu/pred/btb/decoupled_bpred.cc

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -55,10 +55,10 @@ DecoupledBPUWithBTB::DecoupledBPUWithBTB(const DecoupledBPUWithBTBParams &p)
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}
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bpType = DecoupledBTBType;
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// Only add enabled components to the list
58-
if (ubtb->isEnabled()) components.push_back(ubtb);
59-
if (abtb->isEnabled()) components.push_back(abtb);
60-
if (microtage->isEnabled()) components.push_back(microtage);
58+
// if (ubtb->isEnabled()) components.push_back(ubtb);
59+
// if (abtb->isEnabled()) components.push_back(abtb);
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if (mbtb->isEnabled()) components.push_back(mbtb);
61+
if (microtage->isEnabled()) components.push_back(microtage);
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if (tage->isEnabled()) components.push_back(tage);
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if (ras->isEnabled()) components.push_back(ras);
6464
if (ittage->isEnabled()) components.push_back(ittage);

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