add frontend and backend smt (#791)

Co-authored-by: mohaonan <mo.haonan1@sanechips.com.cn>

Author: mhnGitHubz

src/cpu/o3/FuncScheduler.py

@@ -75,6 +75,11 @@ class PAgeSelector(BaseSelector):
 
     piece = Param.Int(2, "number of instructions in a group")
 
+class SMTBasedSelector(BaseSelector):
+    type = 'SMTBasedSelector'
+    cxx_class = 'gem5::o3::SMTBasedSelector'
+    cxx_header = "cpu/o3/issue_queue.hh"
+
 class IssueQue(SimObject):
     type = 'IssueQue'
     cxx_class = 'gem5::o3::IssueQue'
@@ -85,7 +90,7 @@ class IssueQue(SimObject):
     inports = Param.Int(2, "")
     scheduleToExecDelay = Param.Cycles(2, "")
     oports = VectorParam.IssuePort("")
-    sel = Param.BaseSelector(BaseSelector(), "Selector for this IQ (default: age first)")
+    sel = Param.BaseSelector(SMTBasedSelector(), "Selector for this IQ (default: age first)")
 
 class Scheduler(SimObject):
     type = 'Scheduler'

src/cpu/o3/SConscript

@@ -32,7 +32,7 @@ Import('*')
 
 if env['CONF']['TARGET_ISA'] != 'null':
     SimObject('FuncScheduler.py', sim_objects=['FUPool', 'SpecWakeupChannel',
-              'IssuePort', 'IssueQue', 'BaseSelector', 'PAgeSelector', 'Scheduler'])
+              'IssuePort', 'IssueQue', 'BaseSelector', 'PAgeSelector', 'SMTBasedSelector', 'Scheduler'])
     SimObject('FuncUnitConfig.py', sim_objects=[])
     SimObject('BaseO3CPU.py', sim_objects=['BaseO3CPU'], enums=[
         'SMTFetchPolicy', 'SMTQueuePolicy', 'CommitPolicy', 'ROBWalkPolicy', 'ROBCompressPolicy', 'PerfRecord'])

src/cpu/o3/comm.hh

@@ -168,6 +168,12 @@ struct IssueStruct
     DynInstPtr insts[MaxWidth];
 };
 
+struct SquashInfo
+{
+    InstSeqNum squashSn;
+    ThreadID   squashTid;
+};
+
 struct SquashVersion
 {
     uint8_t version;
@@ -246,6 +252,10 @@ struct TimeStruct
         };
         /** Resolved control-flow PCs produced this cycle (fetch buffers/merges). */
         std::vector<ResolvedCFIEntry> resolvedCFIs;  // *F
+
+        unsigned iqCount;
+        unsigned ldstqCount;
+        unsigned robCount;
     };
 
     IewComm iewInfo[MaxThreads]; // iew to rename, fetch

src/cpu/o3/fetch.cc

@@ -148,6 +148,8 @@ Fetch::Fetch(CPU *_cpu, const BaseO3CPUParams &params)
         threads[tid].data = new uint8_t[fetchBufferSize];
     }
 
+    initDecodeScheduler();
+
     // Get the size of an instruction.
     // stallReason size should be the same as decodeWidth,renameWidth,dispWidth
     stallReason.resize(decodeWidth, StallReason::NoStall);
@@ -372,6 +374,41 @@ Fetch::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
     fromCommit = timeBuffer->getWire(-commitToFetchDelay);
 }
 
+void
+Fetch::initDecodeScheduler()
+{
+     // Initialize counters (same as before)
+    lsqCounter = new InstsCounter();
+    iqCounter  = new InstsCounter();
+    robCounter = new InstsCounter();
+    DPRINTF(Fetch, "Initialized SMT Decode Scheduler: 0\n");
+
+    for (ThreadID tid = 0; tid < numThreads; tid++) 
+    {
+        lsqCounter->setCounter(tid, 0);
+        iqCounter->setCounter(tid, 0);
+        robCounter->setCounter(tid, 0);
+    }
+    DPRINTF(Fetch, "Initialized SMT Decode Scheduler: 1\n");
+    
+    if (smtDecodePolicy == "icount") {
+        // Use ROB as default counter for icount
+        decodeScheduler = new ICountScheduler(numThreads, robCounter);
+    }
+    else if (smtDecodePolicy == "delayed") {
+        decodeScheduler = new DelayedICountScheduler(numThreads, robCounter, delayedSchedulerDelay);
+    }
+    else if (smtDecodePolicy == "multi_priority") {
+        decodeScheduler = new MultiPrioritySched(numThreads, {lsqCounter, iqCounter, robCounter});
+    }
+    else {
+        // Default: round-robin like (use delayed with thread cycling)
+        decodeScheduler = new DelayedICountScheduler(numThreads, robCounter, numThreads);
+    }
+
+    DPRINTF(Fetch, "Initialized SMT Decode Scheduler: %s\n", smtDecodePolicy.c_str());
+}
+
 void
 Fetch::setActiveThreads(std::list<ThreadID> *at_ptr)
 {
@@ -1285,6 +1322,32 @@ Fetch::handleInterrupts()
     }
 }
 
+ThreadID
+Fetch::selectUnstalledThread()
+{
+
+    // if (numThreads == 1) {
+    //     return 0;
+    // }
+    for (ThreadID tid = 0; tid < numThreads; ++tid) {
+        if (!stallSig->blockFetch[tid]) {
+            lsqCounter->setCounter(tid, fromIEW->iewInfo[tid].ldstqCount);
+            iqCounter->setCounter(tid, fromIEW->iewInfo[tid].iqCount);
+            robCounter->setCounter(tid, fromIEW->iewInfo[tid].robCount);
+           
+        } else {
+            lsqCounter->setCounter(tid, UINT64_MAX);
+            iqCounter->setCounter(tid, UINT64_MAX);
+            robCounter->setCounter(tid, UINT64_MAX);
+            
+        }
+        DPRINTF(Fetch, "lsqCounter->setCounter: %d iqCounter->setCounter: %d robCounter->setCounter: %d\n",fromIEW->iewInfo[tid].ldstqCount,fromIEW->iewInfo[tid].iqCount,fromIEW->iewInfo[tid].robCount);
+    }
+
+    ThreadID selected = decodeScheduler->getThread();
+    return selected;
+}
+
 void
 Fetch::sendInstructionsToDecode()
 {
@@ -1321,7 +1384,7 @@ Fetch::sendInstructionsToDecode()
         return;
     }
 
-    ThreadID tid = 0; // TODO: smt support
+    ThreadID tid =selectUnstalledThread();
 
     // fetch totally stalled
     if (stallSig->blockFetch[tid]) {

src/cpu/o3/fetch.hh

@@ -65,6 +65,7 @@
 #include "mem/port.hh"
 #include "sim/eventq.hh"
 #include "sim/probe/probe.hh"
+#include "cpu/o3/smt_sched.hh"
 
 namespace gem5
 {
@@ -233,6 +234,18 @@ class Fetch
     /** To probe when a fetch request is successfully sent. */
     ProbePointArg<RequestPtr> *ppFetchRequestSent;
 
+    // SMT Decode Scheduler
+    SMTScheduler* decodeScheduler;
+
+    // Counters from backend structures (to be passed in)
+    InstsCounter* lsqCounter;
+    InstsCounter* iqCounter;
+    InstsCounter* robCounter;
+
+    // Configuration parameters
+    std::string smtDecodePolicy ="multi_priority";
+    int delayedSchedulerDelay;
+
   public:
     /** Fetch constructor. */
     Fetch(CPU *_cpu, const BaseO3CPUParams &params);
@@ -299,6 +312,12 @@ class Fetch
 
     /** For priority-based fetch policies, need to keep update priorityList */
     void deactivateThread(ThreadID tid);
+
+    // Function to initialize scheduler
+    void initDecodeScheduler();
+
+    // Select a thread that is not fetch-blocked, using scheduler
+    ThreadID selectUnstalledThread();
   private:
     /** Reset this pipeline stage */
     void resetStage();

src/cpu/o3/iew.cc

@@ -525,7 +525,7 @@ IEW::squash(ThreadID tid)
 
     for (auto& dp : dispQue) {
         for (auto& it : dp) {
-            if (it->seqNum > fromCommit->commitInfo[tid].doneSeqNum) {
+            if (it->seqNum > fromCommit->commitInfo[tid].doneSeqNum && (it->threadNumber == tid)) {
                 it->setSquashed();
             }
         }
@@ -1533,6 +1533,9 @@ IEW::executeInsts()
     ThreadID tid = *activeThreads->begin();
     toFetch->iewInfo[tid].resolvedCFIs.clear();
 
+    toFetch->iewInfo[tid].ldstqCount=ldstQueue.getCount(tid);
+    toFetch->iewInfo[tid].robCount= rob->getThreadEntries(tid);
+    toFetch->iewInfo[tid].iqCount= scheduler->getIQInsts(tid);
     // Execute/writeback any instructions that are available.
     int insts_to_execute = fromIssue->size;
     fromIssue->size = 0;

src/cpu/o3/inst_queue.cc

@@ -151,7 +151,8 @@ InstructionQueue::InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr,
     scheduler->setCPU(cpu_ptr, &iew_ptr->ldstQueue);
     scheduler->resetDepGraph(numPhysRegs);
     scheduler->setMemDepUnit(memDepUnit);
-
+    scheduler->initIQICountSmtScheduler(numThreads);
+    
     resetState();
 }
 
@@ -1121,7 +1122,9 @@ InstructionQueue::doSquash(ThreadID tid)
 
     DPRINTF(IQ, "[tid:%i] Squashing until sequence number %i!\n",
             tid, squashedSeqNum[tid]);
-    scheduler->doSquash(squashedSeqNum[tid]);
+    squashInfo.squashTid = tid;
+    squashInfo.squashSn  = squashedSeqNum[tid];
+    scheduler->doSquash(squashInfo);
 
     for (auto it = mdpAddrReplayLdInsts.begin(); it != mdpAddrReplayLdInsts.end();) {
         if (!it->inst ||
@@ -1134,7 +1137,7 @@ InstructionQueue::doSquash(ThreadID tid)
     }
 
     for (auto it = nonSpecInsts.begin(); it != nonSpecInsts.end();) {
-        if (it->first > squashedSeqNum[tid]) {
+        if (it->first > squashedSeqNum[tid]  && (it->second->threadNumber == tid)) {
             auto& squashed_inst = it->second;
             if (!squashed_inst->isIssued() ||
                 (squashed_inst->isMemRef() &&

src/cpu/o3/inst_queue.hh

@@ -427,6 +427,7 @@ class InstructionQueue
 
     /** The sequence number of the squashed instruction. */
     InstSeqNum squashedSeqNum[MaxThreads];
+    SquashInfo    squashInfo;
 
     struct IQStats : public statistics::Group
     {