cpu-o3: Add load value prediction framework (#766)

Integrate and resolve code merge conflicts of the load value prediction (LVP) framework from PR #297,
keeping training/prediction/recovery/algorithm paths only, remove Ideal Model code paths to simplify maintenance.

Add IdealConstantLVP with unbounded table as an ideal constant predictor,
to explore the upper bound and parameter space of constant value prediction.

Change-Id: I2f11ea1af963e3dcae82f7380a1e3cf016d7007c

Co-authored-by: Yibo Zhang <yb_zhang@mail.ustc.edu.cn>

Author: happy-lx

configs/example/idealkmhv3.py

@@ -19,6 +19,8 @@
 from common.Caches import *
 from common.xiangshan import *
 
+from m5.objects.ValuePredictor import *
+
 def setKmhV3IdealParams(args, system):
     for cpu in system.cpu:
 
@@ -63,6 +65,9 @@ def setKmhV3IdealParams(args, system):
         cpu.sbufferBankWriteAccurately = True
         cpu.DcacheSetDivNum = 2
 
+        # value predictor
+        cpu.valuePred = IdealConstantLVP()
+
         # lsq
         cpu.LQEntries = 128
         cpu.SQEntries = 64

src/cpu/o3/BaseO3CPU.py

@@ -44,6 +44,7 @@
 from m5.objects.FuncScheduler import *
 #from m5.objects.O3Checker import O3Checker
 from m5.objects.BranchPredictor import *
+from m5.objects.ValuePredictor import *
 from m5.SimObject import *
 
 class SMTFetchPolicy(ScopedEnum):
@@ -254,6 +255,9 @@ def support_take_over(cls):
 
     store_prefetch_train = Param.Bool(True, "Training store prefetcher with store addresses")
 
+    # value predictor
+    valuePred = Param.ValuePredictor(NULL, "valuepred unit")
+
     enable_loadFusion = Param.Bool(False, "Enable load fusion")
 
     enableConstantFolding = Param.Bool(False, "Enable Constant Folding (add-immediate elimination)")

src/cpu/o3/comm.hh

@@ -157,6 +157,8 @@ struct IEWStruct
     bool branchMispredict[MaxThreads];
     bool branchTaken[MaxThreads];
     bool includeSquashInst[MaxThreads];
+
+    bool valuePredictionError[MaxThreads];
 };
 
 struct IssueStruct

src/cpu/o3/commit.cc

@@ -135,6 +135,7 @@ Commit::Commit(CPU *_cpu, branch_prediction::BPredUnit *_bp, const BaseO3CPUPara
       }, "CommitStuckCheckEvent"),
       cpu(_cpu),
       bp(_bp),
+      valuePred(params.valuePred),
       iewToCommitDelay(params.iewToCommitDelay),
       commitToIEWDelay(params.commitToIEWDelay),
       renameToROBDelay(params.renameToROBDelay),
@@ -294,6 +295,8 @@ Commit::CommitStats::CommitStats(CPU *cpu, Commit *commit)
                "Number of squash due to branch"),
       ADD_STAT(squashDueToOrderViolation, statistics::units::Count::get(),
                "Number of squash due to order violation"),
+      ADD_STAT(squashDueToValuePrediction, statistics::units::Count::get(),
+               "Number of squash due to value prediction"),
       ADD_STAT(squashDueToTrap, statistics::units::Count::get(),
                "Number of squash due to trap"),
       ADD_STAT(squashDueToTC, statistics::units::Count::get(),
@@ -691,6 +694,9 @@ Commit::squashAll(ThreadID tid)
     rob->squash(squashed_inst, tid);
     changedROBNumEntries[tid] = true;
 
+    if (valuePred)
+        valuePred->squash(squashed_inst);
+
     // Send back the sequence number of the squashed instruction.
     toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
     toIEW->commitInfo[tid].doneMemSeqNum = squashed_inst;
@@ -1034,6 +1040,11 @@ Commit::commit()
                     fromIEW->mispredictInst[tid]->pcState().instAddr(),
                     fromIEW->squashedSeqNum[tid]);
                 stats.squashDueToBranch++;
+            } else if (fromIEW->valuePredictionError[tid]) {
+                DPRINTF(Commit,
+                    "[tid:%i] Squashing due to value prediction error [sn:%llu]\n",
+                    tid, fromIEW->squashedSeqNum[tid]);
+                stats.squashDueToValuePrediction++;
             } else {
                 DPRINTF(Commit,
                     "[tid:%i] Squashing due to order violation [sn:%llu]\n",
@@ -1061,6 +1072,9 @@ Commit::commit()
             rob->squash(squashed_inst, tid);
             changedROBNumEntries[tid] = true;
 
+            if (valuePred)
+                valuePred->squash(squashed_inst);
+
             toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
             toIEW->commitInfo[tid].doneMemSeqNum = squashed_inst;
 
@@ -1815,6 +1829,25 @@ Commit::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
     if (head_inst->isHtmStart())
         iewStage->setLastRetiredHtmUid(tid, head_inst->getHtmTransactionUid());
 
+    if (valuePred && head_inst->canLVP() && (inst_fault == NoFault)) {
+        valuepred::VPUpdateMetaData *updateMetaData = valuepred::
+                    VPDataStructFactory::buildUpdateMetaData(valuePred->getValuePredictorType());
+        updateMetaData->pc = head_inst->getPC();
+        updateMetaData->seq_no = head_inst->seqNum;
+        updateMetaData->actualValue = head_inst->actualValue;
+        updateMetaData->isMisprediction = head_inst->vpMisprediction;
+        valuePred->updateValuePredictor(updateMetaData);
+        valuePred->stats.VPsupported++;
+        if (head_inst->vpResult.speculative) {
+            valuePred->stats.VPpredicted++;
+            if (!head_inst->vpMisprediction) {
+                valuePred->stats.VPcorrected++;
+            }
+        }
+
+        delete updateMetaData;
+    }
+
     // Finally clear the head ROB entry.
     rob->retireHead(tid);
 

src/cpu/o3/commit.hh

@@ -64,6 +64,7 @@
 #include "cpu/pred/general_arch_db.hh"
 #include "cpu/pred/stream/decoupled_bpred.hh"
 #include "cpu/timebuf.hh"
+#include "cpu/valuepred/valuepred_unit.hh"
 #include "enums/CommitPolicy.hh"
 #include "sim/arch_db.hh"
 #include "sim/probe/probe.hh"
@@ -441,6 +442,9 @@ class Commit
 
     branch_prediction::BPredUnit *bp;
 
+    /** Value predictor */
+    valuepred::VPUnit *valuePred;
+
     /** Vector of all of the threads. */
     std::vector<ThreadState *> thread;
 
@@ -633,6 +637,7 @@ class Commit
 
         statistics::Scalar squashDueToBranch;
         statistics::Scalar squashDueToOrderViolation;
+        statistics::Scalar squashDueToValuePrediction;
         statistics::Scalar squashDueToTrap;
         statistics::Scalar squashDueToTC;
         statistics::Scalar squashDueToSquashAfter;

src/cpu/o3/cpu.cc

@@ -131,7 +131,8 @@ CPU::CPU(const BaseO3CPUParams &params)
       issueWidth(params.decodeWidth),
       enableConstantFolding(params.enableConstantFolding),
       enableMovImmElimination(params.enableMovImmElimination),
-      cpuStats(this)
+      cpuStats(this),
+      valuePred(params.valuePred)
 {
     fatal_if(FullSystem && params.numThreads > 1,
             "SMT is not supported in O3 in full system mode currently.");

src/cpu/o3/cpu.hh

@@ -71,6 +71,7 @@
 #include "cpu/o3/thread_state.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/timebuf.hh"
+#include "cpu/valuepred/valuepred_unit.hh"
 #include "mem/cache/prefetch/base.hh"
 #include "params/BaseO3CPU.hh"
 #include "sim/process.hh"
@@ -739,6 +740,15 @@ class CPU : public BaseCPU
 
     //difftest virtual function
     void readGem5Regs() override;
+
+  private:
+    /** Value predictor */
+    valuepred::VPUnit *valuePred;
+
+  public:
+    bool isValuePredictorEnabled() const { return valuePred != nullptr; }
+
+    valuepred::VPUnit *getValuePredictor() const { return valuePred; }
 };
 
 } // namespace o3

src/cpu/o3/dyn_inst.hh

@@ -68,6 +68,7 @@
 #include "cpu/reg_class.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/translation.hh"
+#include "cpu/valuepred/valuepred_metadata.hh"
 #include "debug/CommitTrace.hh"
 #include "debug/DecoupleBP.hh"
 #include "debug/HtmCpu.hh"
@@ -744,6 +745,7 @@ class DynInst : public ExecContext, public RefCounted
     bool isHInst()        const { return staticInst->isHInst(); }
     bool isStore()        const { return staticInst->isStore(); }
     bool isAtomic()       const { return staticInst->isAtomic(); }
+    bool isLoadReserved() const { return staticInst->isLoadReserved(); }
     bool isStoreConditional() const
     { return staticInst->isStoreConditional(); }
     bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
@@ -1649,6 +1651,17 @@ class DynInst : public ExecContext, public RefCounted
 
     /** get golden */
     uint8_t *getGolden() { return goldenData; }
+
+    /** value prediction */
+    valuepred::VPResult vpResult = {false, 0xdeadbeefULL};
+
+    RegVal actualValue = 0xdeadbeefULL;
+    bool vpMisprediction = false;
+    bool vpSupported = false;
+
+    bool canLVP(){
+        return isLoad() && !isVector() && !isLoadReserved();
+    }
 };
 
 } // namespace o3

src/cpu/o3/fetch.cc

@@ -110,7 +110,8 @@ Fetch::Fetch(CPU *_cpu, const BaseO3CPUParams &params)
       numThreads(params.numThreads),
       numFetchingThreads(params.smtNumFetchingThreads),
       icachePort(this, _cpu),
-      finishTranslationEvent(this), fetchStats(_cpu, this)
+      finishTranslationEvent(this), fetchStats(_cpu, this),
+      valuePred(params.valuePred)
 {
     if (numThreads > MaxThreads)
         fatal("numThreads (%d) is larger than compiled limit (%d),\n"
@@ -1921,6 +1922,17 @@ Fetch::processSingleInstruction(ThreadID tid, PCStateBase &pc,
     // Update the main PC state for the next instruction.
     set(pc, *next_pc);
 
+    // Do the value prediction
+    if (valuePred && instruction->canLVP()) {
+        valuepred::VPPredMetaData* vpPredMetaData = valuepred::VPDataStructFactory::
+                                                        buildPredMetaData(valuePred->getValuePredictorType());
+
+        vpPredMetaData->pc = instruction->getPC();
+        vpPredMetaData->seq_no = instruction->seqNum;
+        instruction->vpResult = valuePred->valuePredict(vpPredMetaData);
+        delete vpPredMetaData;
+    }
+
     return predictedBranch;
 }
 

src/cpu/o3/fetch.hh

@@ -59,6 +59,7 @@
 #include "cpu/pred/btb/decoupled_bpred.hh"
 #include "cpu/timebuf.hh"
 #include "cpu/translation.hh"
+#include "cpu/valuepred/valuepred_unit.hh"
 #include "enums/SMTFetchPolicy.hh"
 #include "mem/packet.hh"
 #include "mem/port.hh"
@@ -1116,6 +1117,9 @@ public:
   private:
 
     bool waitForVsetvl = false;
+
+    /** Value predictor */
+    valuepred::VPUnit *valuePred;
 };
 
 } // namespace o3