cpu-o3: simplify fetch， only support decoupled BTB mode (#721)

* cpu-o3: simplify fetch， only support decoupled BTB mode

Change-Id: If39d11a07088d4f9237d5bf6c30a9dd8f53a1436

* cpu-o3: delete isDecoupledFrontend()

Change-Id: Ibac84ee677f597f90bc7ff70a0ff6a1b1d108586

* cpu-o3: fetch: move updateBranchPredictors to tick() start

now we can update BPU to supply fetch first, then let fetch to consume this ftq entry.

Change-Id: I922b899d7626e010b5f3589b39ad4c6cec6f7c2b

* cpu-o3: fetch: split usedUpFetchTargets

This update introduces a clearer separation of fetch state management by replacing the `usedUpFetchTargets` flag with `needFtqSupply` and `exhaustedFtqEntry`. The new flags enhance clarity in FTQ supply logic, ensuring that fetch operations correctly handle the availability of fetch targets. Additionally, the `trySupplyFtq` method is added to streamline FTQ supply attempts, improving overall fetch efficiency and maintainability.

Change-Id: Ie17a13ebf64aea7bd68f3c4c50917b3e3c9b830a

* cpu-o3: test remove ftq code

I thinks we can delete this, run spec06 for try.

Change-Id: If21eca420d21d8ca038dc1065e144fe346a23131

* cpu-o3: refactor fetch state management and FTQ handling

1. removes the `needFtqSupply` and `exhaustedFtqEntry` flags from the Fetch class, simplifying the fetch state management.
2. The logic for FTQ supply is streamlined, ensuring that fetch operations directly check the availability of fetch targets without maintaining additional state.
3. The `trySupplyFtq` method is also removed, as the fetch now operates in a head-driven FIFO manner. This change enhances clarity and maintainability of the fetch logic.

Change-Id: I7a8b312785a7cce526192de7125cea458b979c0e

* cpu-o3: fetch ftq rename some functions

1. Reset the instruction count for FTQ entries in multiple locations to ensure accurate tracking of fetched instructions.
2. Replace deprecated `updateBranchPredictors` method with direct calls to `dbpbtb->tick()` for improved clarity and maintainability.
3. Refactor fetch logic to utilize `ftqHasHead()` and `ftqHead()` methods, enhancing the readability of fetch target availability checks.
4. Introduce `consumeFetchTarget` method in the decoupled branch predictor to streamline the handling of consumed fetch targets.

These changes improve the overall structure and efficiency of the fetch stage, ensuring better integration with the branch predictor and FTQ management.

Change-Id: I7a8b312785a7cce526192de7125cea458b979c0e

* cpu-o3: remove decoupledPredict in fetch

1. Refactor the next PC prediction logic to directly compute from the FTQ head entry, improving clarity and efficiency.
2. Introduce checks for the current PC against the predicted takenPC, streamlining the fetch process for taken branches.
3. Update the handling of microops to ensure they advance the program counter correctly, maintaining accurate instruction flow.

These changes improve the overall structure and efficiency of the fetch stage, ensuring better integration with the branch predictor and FTQ management.

Change-Id: Iaed922245a386b695499799c9e0a3947208e0524

* cpu-o3: add some docs

Change-Id: I56c36d4757b2a78ad193225f6eef302fd2c986ad

* cpu-o3: remove useless source code in v3 BPU

Change-Id: I1c6093c1f63036b6346838572229e4440726d7f9

* util:  remove unused scripts

- Updated `gem5-vec.cfg` to remove DRAMsim3 configuration.
- Changed `gem5.cfg` to use `kmhv3.py` instead of `fs.py` for task execution.
- Removed deprecated options from `Options.py` related to branch prediction.
- Adjusted `xiangshan.py` to enforce BTB-only branch prediction and streamline configuration.
- Deleted unused `fs.py` file and various scripts to clean up the repository.
- Updated example configurations to align with new branch prediction policies.

These changes enhance clarity and maintainability of the configuration files while ensuring compliance with the current branch prediction strategy.

Change-Id: I1c6093c1f63036b6346838572229e4440726d7f9

---------

Co-authored-by: Yakkhini <59007159+Yakkhini@users.noreply.github.com>

Author: jensen-yan

.github/workflows/autotest/gem5-vec.cfg

@@ -43,7 +43,6 @@ fs_path = ./configs/example/kmhv2.py --enable-riscv-vector --restore-rvv-cpt
 task ={set_env} && ./build/RISCV/gem5.opt \
     --outdir=$sublog$ \
     {fs_path} \
-	--dramsim3-ini=./ext/dramsim3/xiangshan_configs/xiangshan_DDR4_8Gb_x8_3200_2ch.ini \
 	--raw-cpt --generic-rv-cpt=$binfile$ 
 post-task = 
 except-task = echo gem5 running error!

.github/workflows/autotest/gem5.cfg

@@ -169,27 +169,10 @@ pre-task =
 task = {set_var} && \
     ./build/RISCV/gem5.opt \
     --outdir=$sublog$ \
-    ./configs/example/fs.py \
+    ./configs/example/kmhv3.py \
     --enable-difftest --difftest-ref-so {ref_so_path} \
-    --xiangshan-system --cpu-type=DerivO3CPU \
-    --mem-size=8GB \
-    --caches --cacheline_size=64 \
-    --l1i_size=64kB --l1i_assoc=8 \
-    --l1d_size=64kB --l1d_assoc=4 \
-    --l1d-hwp-type=XSCompositePrefetcher \
-    --short-stride-thres=0 \
-    --l2cache --l2_size=1MB --l2_assoc=8 \
-    --l3cache --l3_size=16MB --l3_assoc=16 \
-    --l1-to-l2-pf-hint \
-    --l2-hwp-type=PrefetcherForwarder \
-    --l2-wrapper-hwp-type=WorkerPrefetcher \
-    --l2-to-l3-pf-hint \
-    --l3-hwp-type=WorkerPrefetcher \
-    --mem-type=DRAMsim3 \
-    --dramsim3-ini=./ext/dramsim3/xiangshan_configs/xiangshan_DDR4_8Gb_x8_3200_2ch.ini \
     --generic-rv-cpt=$binfile$ \
     --gcpt-restorer={gcpt_path} \
-    --bp-type=DecoupledBPUWithFTB --enable-loop-predictor --enable-jump-ahead-predictor \
     --warmup-insts=800 --warmup-insts-no-switch=50000010 --maxinsts=100000010
 post-task = echo run successfully at $binfile$
 except-task = echo gem5 running error at $binfile$!

.github/workflows/gem5-ideal-btb-perf-nosc.yml

@@ -279,16 +279,6 @@ def addCommonOptions(parser, configure_xiangshan=False):
                         help="enable bp database for specified subdatabase, "
                         "basic branch trace is enabled by default even without specifying, "
                         "available subdatabase: basic, tage, ras, loop")
-    parser.add_argument("--disable-sc", default=False, action="store_true",
-                        help="disable SC (enabled by default, only for FTBTAGE)")
-    parser.add_argument("--disable-mgsc", default=False, action="store_true",
-                        help="disable MGSC (only for BTBTAGE)")
-    parser.add_argument("--enable-loop-buffer", default=False, action="store_true",
-                        help="enable loop buffer (only for ftb branch predictor)")
-    parser.add_argument("--enable-loop-predictor", default=False, action="store_true",
-                        help="enable loop predictor (only for ftb branch predictor)")
-    parser.add_argument("--enable-jump-ahead-predictor", default=False, action="store_true",
-                        help="enable jump ahead predictor (only for ftb branch predictor)")
 
     parser.add_argument("--list-rp-types",
                         action=ListRP, nargs=0,

configs/common/Options.py

@@ -329,50 +329,27 @@ def build_xiangshan_system(args):
             print(f"Trace mode: CPU {cpu.cpu_id} configured with {mode_str} translation")
 
     # configure BP
-    args.enable_loop_predictor = True
-    if args.enable_riscv_vector:
-        args.enable_loop_buffer = True
-
     for i in range(np):
         if args.kmh_align:
             test_sys.cpu[i].enable_storeSet_train = False
 
-        if args.bp_type is None or args.bp_type == 'DecoupledBPUWithFTB' or args.bp_type == 'DecoupledBPUWithBTB':
-            enable_bp_db = len(args.enable_bp_db) > 1
-            if enable_bp_db:
-                bp_db_switches = args.enable_bp_db[1] + ['basic']
-                print("BP db switches:", bp_db_switches)
-            else:
-                bp_db_switches = []
-            # for DecoupledBPUWithBTB, loop predictor and jump ahead predictor are not supported
-            #if args.bp_type == 'DecoupledBPUWithBTB':
-            if args.enable_loop_predictor or args.enable_loop_buffer:
-                print("loop predictor and loop buffer not supported for DecoupledBPUWithBTB")
-                args.enable_loop_predictor = False
-                args.enable_loop_buffer = False
-            if args.enable_jump_ahead_predictor:
-                print("jump ahead predictor not supported for DecoupledBPUWithBTB")
-                args.enable_jump_ahead_predictor = False
-
-            BPClass = DecoupledBPUWithBTB() if args.bp_type == 'DecoupledBPUWithBTB' else DecoupledBPUWithFTB()
-            test_sys.cpu[i].branchPred = BPClass(
-                                            bpDBSwitches=bp_db_switches,
-                                            enableLoopBuffer=args.enable_loop_buffer,
-                                            enableLoopPredictor=args.enable_loop_predictor,
-                                            enableJumpAheadPredictor=args.enable_jump_ahead_predictor
-                                            )
-            test_sys.cpu[i].branchPred.tage.enableSC = not args.disable_sc
-            test_sys.cpu[i].branchPred.isDumpMisspredPC = True
+        if args.bp_type != 'DecoupledBPUWithBTB':
+            fatal(
+                "Only --bp-type=DecoupledBPUWithBTB is supported for Xiangshan in this repo "
+                f"(got --bp-type={args.bp_type})."
+            )
 
+        enable_bp_db = len(args.enable_bp_db) > 1
+        if enable_bp_db:
+            bp_db_switches = args.enable_bp_db[1] + ['basic']
+            print("BP db switches:", bp_db_switches)
         else:
-            BPClass = ObjectList.bp_list.get(args.bp_type)
-            test_sys.cpu[i].branchPred = BPClass()
-
-        if args.indirect_bp_type:
-            IndirectBPClass = ObjectList.indirect_bp_list.get(
-                args.indirect_bp_type)
-            test_sys.cpu[i].branchPred.indirectBranchPred = \
-                    IndirectBPClass()
+            bp_db_switches = []
+
+        test_sys.cpu[i].branchPred = DecoupledBPUWithBTB(
+            bpDBSwitches=bp_db_switches,
+        )
+        test_sys.cpu[i].branchPred.isDumpMisspredPC = True
 
     # configure memory related
     if args.mem_type == 'DRAMsim3':