cpu-o3: add support for choice MBTB basetable in branch predict

Change-Id: Iebed52eb9e3a60ac5ef3bbc0e96095d2d16ef0fa

Author: Cao Jiaming

configs/example/kmhv3.py

@@ -108,6 +108,10 @@ def setKmhV3Params(args, system):
             cpu.branchPred.mgsc.enabled = False
             cpu.branchPred.ras.enabled = True
 
+            usingMbtbBaseEiterTage = True
+            cpu.branchPred.mbtb.usingMbtbBaseEiterTage = usingMbtbBaseEiterTage
+            cpu.branchPred.tage.usingMbtbBaseEiterTage = usingMbtbBaseEiterTage
+
         # l1 cache per core
         if args.caches:
             cpu.icache.size = '64kB'

src/cpu/pred/BranchPredictor.py

@@ -985,6 +985,7 @@ class MBTB(TimedBaseBTBPredictor):
     blockSize = 32  # max 64 byte block, 32 byte aligned
     # MBTB is always half-aligned - no parameter needed
     victimCacheSize = Param.Unsigned(0, "Number of entries in the victim cache")
+    usingMbtbBaseEiterTage = Param.Bool(True, "Whether using MBTB basetable either TAGE ")
 
 class AheadBTB(TimedBaseBTBPredictor):
     type = 'AheadBTB'
@@ -1060,6 +1061,7 @@ class BTBTAGE(TimedBaseBTBPredictor):
     numBanks = Param.Unsigned(4, "Number of banks for bank conflict simulation")
     enableBankConflict = Param.Bool(True, "Enable bank conflict simulation")
     numDelay = 2
+    usingMbtbBaseEiterTage = Param.Bool(True, "Whether using MBTB basetable either TAGE ")
 
 class MicroTAGE(BTBTAGE):
     """A smaller TAGE predictor configuration to assist uBTB"""

src/cpu/pred/btb/btb_tage.cc

@@ -91,6 +91,7 @@ indexShift(bankBaseShift + ceilLog2(p.numBanks)),
 enableBankConflict(p.enableBankConflict),
 lastPredBankId(0),
 predBankValid(false),
+usingBasetable( !p.usingMbtbBaseEiterTage),
 tageStats(this, p.numPredictors, p.numBanks)
 {
     this->needMoreHistories = p.needMoreHistories;
@@ -269,8 +270,9 @@ BTBTAGE::generateSinglePrediction(const BTBEntry &btb_entry,
     // Use base table instead of btb_entry.ctr
     Addr base_idx = getBaseTableIndex(startPC);
     unsigned branch_idx = getBranchIndexInBlock(btb_entry.pc, startPC);
-    //bool base_taken = getDelay() != 0 ? baseTable[base_idx][branch_idx] >= 0 : btb_entry.ctr >= 0;
-    bool base_taken = btb_entry.ctr >= 0;
+    bool base_taken = getDelay() != 0 ? (usingBasetable ? baseTable[base_idx][branch_idx] >= 0 : btb_entry.ctr >= 0)
+                                                                                     : btb_entry.ctr >= 0;
+    //bool base_taken = btb_entry.ctr >= 0;
     bool alt_pred = alt_provided ? alt_taken : base_taken; // if alt provided, use alt prediction, otherwise use base
 
     // use_alt_on_na gating: when provider weak, consult per-PC counter

src/cpu/pred/btb/btb_tage.hh

@@ -315,6 +315,7 @@ class BTBTAGE : public TimedBaseBTBPredictor
     // Track last prediction bank for conflict detection
     unsigned lastPredBankId;         // Bank ID of last prediction
     bool predBankValid;              // Whether lastPredBankId is valid
+    bool usingBasetable;          // Whether using basetable for either MBTB or TAGE
 
 #ifdef UNIT_TEST
     typedef uint64_t Scalar;

src/cpu/pred/btb/mbtb.cc

@@ -81,6 +81,7 @@ MBTB::MBTB(const Params &p)
     numEntries(p.numEntries),
     numWays(p.numWays),
     tagBits(p.tagBits),
+    usingBasetable(p.usingMbtbBaseEiterTage),
     btbStats(this, p.numWays)
 {
     // MBTB doesn't support ahead-pipelined stages
@@ -696,16 +697,19 @@ MBTB::update(const FetchStream &stream)
     // 1. Check prediction hit status, for stats recording
     checkPredictionHit(stream,
         std::static_pointer_cast<BTBMeta>(stream.predMetas[getComponentIdx()]).get());
-
-    // only update btb entry for control squash T-> NT or NT -> T
-    // if (stream.squashType == SQUASH_CTRL) {
-    //     warn_if(stream.exeBranchInfo.pc > stream.updateEndInstPC, "exeBranchInfo.pc > updateEndInstPC");
-    //     updateBTBEntry(stream.exeBranchInfo, stream);
-    // }
-    auto entries_need_update = prepareUpdateEntries(stream);
-    for (auto &entry : entries_need_update) {
-        updateBTBEntry(entry, stream);
+    if (!usingBasetable) {
+        // only update btb entry for control squash T-> NT or NT -> T
+        if (stream.squashType == SQUASH_CTRL) {
+            warn_if(stream.exeBranchInfo.pc > stream.updateEndInstPC, "exeBranchInfo.pc > updateEndInstPC");
+            updateBTBEntry(stream.exeBranchInfo, stream);
+        }
+    }else {
+        auto entries_need_update = prepareUpdateEntries(stream);
+        for (auto &entry : entries_need_update) {
+            updateBTBEntry(entry, stream);
+        }
     }
+
 }
 
 

src/cpu/pred/btb/mbtb.hh

@@ -395,6 +395,7 @@ class MBTB : public TimedBaseBTBPredictor
     /** Address calculation masks and shifts */
     Addr idxMask;          // Mask for extracting index bits
     unsigned tagBits;      // Number of tag bits
+    bool usingBasetable;   // Whether using basetable for either MBTB or TAGE
     Addr tagMask;          // Mask for extracting tag bits
     unsigned idxShiftAmt;  // Amount to shift PC for index
     unsigned tagShiftAmt;  // Amount to shift PC for tag