|
| 1 | +import argparse |
| 2 | +import sys |
| 3 | + |
| 4 | +import m5 |
| 5 | +from m5.defines import buildEnv |
| 6 | +from m5.objects import * |
| 7 | +from m5.util import addToPath, fatal, warn |
| 8 | +from m5.util.fdthelper import * |
| 9 | + |
| 10 | +addToPath('../') |
| 11 | + |
| 12 | +from ruby import Ruby |
| 13 | + |
| 14 | +from common.FSConfig import * |
| 15 | +from common.SysPaths import * |
| 16 | +from common.Benchmarks import * |
| 17 | +from common import Simulation |
| 18 | +from common.Caches import * |
| 19 | +from common.xiangshan import * |
| 20 | + |
| 21 | + |
| 22 | +def setKmhV3Params(args, system): |
| 23 | + for cpu in system.cpu: |
| 24 | + |
| 25 | + # fetch (idealfetch not care) |
| 26 | + cpu.mmu.itb.size = 96 |
| 27 | + cpu.fetchWidth = 32 |
| 28 | + cpu.iewToFetchDelay = 2 # for resolved update, should train branch after squash |
| 29 | + cpu.commitToFetchDelay = 2 |
| 30 | + cpu.fetchQueueSize = 64 |
| 31 | + cpu.fetchToDecodeDelay = 2 |
| 32 | + |
| 33 | + # decode |
| 34 | + cpu.decodeWidth = 8 |
| 35 | + cpu.enable_loadFusion = False |
| 36 | + cpu.enableConstantFolding = False |
| 37 | + |
| 38 | + # rename |
| 39 | + cpu.renameWidth = 8 |
| 40 | + cpu.numPhysIntRegs = 224 |
| 41 | + cpu.numPhysFloatRegs = 256 |
| 42 | + cpu.enable_storeSet_train = False |
| 43 | + |
| 44 | + # dispatch |
| 45 | + cpu.enableDispatchStage = False |
| 46 | + cpu.numDQEntries = [8, 8, 8] |
| 47 | + cpu.dispWidth = [8, 8, 8] |
| 48 | + |
| 49 | + # scheduler |
| 50 | + cpu.scheduler = KMHV3Scheduler() |
| 51 | + cpu.scheduler.disableAllRegArb() |
| 52 | + cpu.scheduler.enableMainRdpOpt = False |
| 53 | + cpu.scheduler.intRegfileBanks = 1 |
| 54 | + # intiq0 |
| 55 | + cpu.scheduler.IQs[0].oports[0].rp = [IntRD(0, 0), IntRD(1, 0)] |
| 56 | + cpu.scheduler.IQs[0].oports[1].rp = [IntRD(0, 1), IntRD(1, 1)] |
| 57 | + |
| 58 | + # intiq1 |
| 59 | + cpu.scheduler.IQs[1].oports[0].rp = [IntRD(2, 0), IntRD(3, 0)] |
| 60 | + cpu.scheduler.IQs[1].oports[1].rp = [IntRD(2, 1), IntRD(3, 1)] |
| 61 | + |
| 62 | + # intiq2 |
| 63 | + cpu.scheduler.IQs[2].oports[0].rp = [IntRD(4, 0), IntRD(5, 0)] |
| 64 | + cpu.scheduler.IQs[2].oports[1].rp = [IntRD(4, 1), IntRD(5, 1)] |
| 65 | + |
| 66 | + # rob |
| 67 | + cpu.commitWidth = 8 |
| 68 | + cpu.squashWidth = 8 |
| 69 | + cpu.RobCompressPolicy = 'none' |
| 70 | + cpu.numROBEntries = 352 |
| 71 | + cpu.CROB_instPerGroup = 2 # 1 if not using ROB compression |
| 72 | + |
| 73 | + # lsu |
| 74 | + cpu.StoreWbStage = 4 |
| 75 | + cpu.EnableLdMissReplay = True |
| 76 | + cpu.EnablePipeNukeCheck = True |
| 77 | + cpu.BankConflictCheck = True |
| 78 | + cpu.sbufferBankWriteAccurately = False |
| 79 | + |
| 80 | + # lsq |
| 81 | + cpu.LQEntries = 120 |
| 82 | + cpu.SQEntries = 64 |
| 83 | + cpu.RARQEntries = 96 |
| 84 | + cpu.RAWQEntries = 56 |
| 85 | + cpu.LoadCompletionWidth = 8 |
| 86 | + cpu.StoreCompletionWidth = 4 |
| 87 | + cpu.RARDequeuePerCycle = 4 |
| 88 | + cpu.RAWDequeuePerCycle = 4 |
| 89 | + cpu.SbufferEntries = 16 |
| 90 | + cpu.SbufferEvictThreshold = 7 |
| 91 | + cpu.store_prefetch_train = False |
| 92 | + |
| 93 | + # branch predictor |
| 94 | + if args.bp_type == 'DecoupledBPUWithBTB': |
| 95 | + cpu.branchPred.mgsc.enableMGSC = not args.disable_mgsc |
| 96 | + cpu.branchPred.ftq_size = 256 |
| 97 | + cpu.branchPred.fsq_size = 256 |
| 98 | + |
| 99 | + # l1 cache per core |
| 100 | + if args.caches: |
| 101 | + cpu.icache.size = '64kB' |
| 102 | + cpu.dcache.size = '64kB' |
| 103 | + cpu.dcache.tag_load_read_ports = 3 |
| 104 | + cpu.dcache.mshrs = 16 |
| 105 | + |
| 106 | + # l2 caches |
| 107 | + if args.l2cache: |
| 108 | + for i in range(args.num_cpus): |
| 109 | + if args.classic_l2: |
| 110 | + system.l2_caches[i].slice_num = 4 |
| 111 | + system.l2_caches[i].wpu = NULL |
| 112 | + else: |
| 113 | + l2_wrapper = system.l2_wrappers[i] |
| 114 | + l2_wrapper.data_sram_banks = 1 |
| 115 | + l2_wrapper.dir_sram_banks = 1 |
| 116 | + l2_wrapper.pipe_dir_write_stage = 3 |
| 117 | + l2_wrapper.dir_read_bypass = False |
| 118 | + for j in range(args.l2_slices): |
| 119 | + l2_wrapper.slices[j].inner_cache.wpu = NULL |
| 120 | + system.tol2bus_list[i].forward_latency = 3 # 3->0 |
| 121 | + system.tol2bus_list[i].response_latency = 3 # 3->0 |
| 122 | + system.tol2bus_list[i].hint_wakeup_ahead_cycles = 2 # 2->0 |
| 123 | + |
| 124 | + # Enable dual-port for DCache → L2 communication |
| 125 | + # ReqLayer[0]: ICache+DCache+ITB+DTB → L2, allow 2 requests per cycle |
| 126 | + # RespLayer[1]: L2 → DCache, allow 2 responses per cycle |
| 127 | + # system.tol2bus_list[i].layer_bandwidth_configs = [ |
| 128 | + # LayerBandwidthConfig(direction="req", port_index=0, max_per_cycle=2), |
| 129 | + # LayerBandwidthConfig(direction="resp", port_index=1, max_per_cycle=2), |
| 130 | + # ] |
| 131 | + |
| 132 | + # l3 cache |
| 133 | + if args.l3cache: |
| 134 | + system.l3.mshrs = 64 |
| 135 | + |
| 136 | +if __name__ == '__m5_main__': |
| 137 | + FutureClass = None |
| 138 | + |
| 139 | + args = xiangshan_system_init() |
| 140 | + |
| 141 | + assert not args.external_memory_system |
| 142 | + |
| 143 | + # Set default bp_type based on ideal_kmhv3 flag |
| 144 | + # If user didn't specify bp_type, set default based on ideal_kmhv3 |
| 145 | + args.bp_type = 'DecoupledBPUWithBTB' |
| 146 | + args.l2_size = '2MB' |
| 147 | + |
| 148 | + # Match the memories with the CPUs, based on the options for the test system |
| 149 | + TestMemClass = Simulation.setMemClass(args) |
| 150 | + |
| 151 | + test_sys = build_xiangshan_system(args) |
| 152 | + # Set ideal parameters here with the highest priority, over command-line arguments |
| 153 | + setKmhV3Params(args, test_sys) |
| 154 | + |
| 155 | + root = Root(full_system=True, system=test_sys) |
| 156 | + |
| 157 | + Simulation.run_vanilla(args, root, test_sys, FutureClass) |
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