Resolve update mtbt and tage (#621)

* cpu-o3: only train single fetch block per cycle

Change-Id: I75c3f5f704e39ac4dfd16909ce5da365a2de6a91

* cpu-o3: only enable ubtb,mbtb,tage now

for tage aligning

Change-Id: I41078918deeb1b6a514bcfb0bb5df2df578910d0

* cpu-o3: tage, mbtb use resolve update now

Change-Id: I732d89766545b668bfce47ffe6be9f9b7161d569

---------

Co-authored-by: Yakkhini <59007159+Yakkhini@users.noreply.github.com>

Author: jensen-yan

configs/example/kmhv3.py

@@ -94,14 +94,17 @@ def setKmhV3Params(args, system):
             cpu.branchPred.ftq_size = 256
             cpu.branchPred.fsq_size = 256
 
+            cpu.branchPred.mbtb.resolvedUpdate = True
+            cpu.branchPred.tage.resolvedUpdate = True
+
             cpu.branchPred.ubtb.enabled = True
-            cpu.branchPred.abtb.enabled = True
+            cpu.branchPred.abtb.enabled = False
             cpu.branchPred.microtage.enabled = False
             cpu.branchPred.mbtb.enabled = True
             cpu.branchPred.tage.enabled = True
-            cpu.branchPred.ittage.enabled = True
-            cpu.branchPred.mgsc.enabled = True
-            cpu.branchPred.ras.enabled = True
+            cpu.branchPred.ittage.enabled = False
+            cpu.branchPred.mgsc.enabled = False
+            cpu.branchPred.ras.enabled = False
 
         # l1 cache per core
         if args.caches:

src/cpu/o3/iew.cc

@@ -1566,7 +1566,7 @@ IEW::SquashCheckAfterExe(DynInstPtr inst)
     uint64_t fsqId = inst->getFsqId();
     uint64_t pc = inst->getPC();
     bool found = false;
-    for (auto &entry : toFetch->iewInfo[tid].resolveQueue) {
+    for (auto &entry : resolveQueue) {
         if (entry.resolvedFSQId == fsqId) {
             entry.resolvedInstPC.push_back(pc);
             found = true;
@@ -1577,7 +1577,7 @@ IEW::SquashCheckAfterExe(DynInstPtr inst)
         ResolveQueueEntry newEntry;
         newEntry.resolvedFSQId = fsqId;
         newEntry.resolvedInstPC.push_back(pc);
-        toFetch->iewInfo[tid].resolveQueue.push_back(newEntry);
+        resolveQueue.push_back(newEntry);
     }
 
     if (!fetchRedirect[tid] ||
@@ -1793,6 +1793,13 @@ IEW::executeInsts()
         }
     }
 
+    sortResolveQueue();
+    if (!resolveQueue.empty()) {
+        ResolveQueueEntry entry = resolveQueue.back();
+        resolveQueue.pop_back();
+        toFetch->iewInfo[tid].resolveQueue.push_back(entry);
+    }
+
     ldstQueue.executePipeSx();
 
     // Update and record activity if we processed any instructions.

src/cpu/o3/iew.hh

@@ -494,6 +494,13 @@ class IEW
     /** Maximum size of the skid buffer. */
     unsigned skidBufferMax;
 
+    std::vector<ResolveQueueEntry> resolveQueue;
+    static inline bool resolveQueueEntryCompare(const ResolveQueueEntry &a, const ResolveQueueEntry &b)
+    {
+        return a.resolvedFSQId > b.resolvedFSQId;
+    };
+    inline void sortResolveQueue() { std::sort(resolveQueue.begin(), resolveQueue.end(), resolveQueueEntryCompare); };
+
 
     struct IEWStats : public statistics::Group
     {