fix(CoupledL2): fix l2MissMatch io compilation error (OpenXiangShan#456)

Author: Ma-YX

src/main/scala/coupledL2/CoupledL2.scala

@@ -562,19 +562,18 @@ abstract class CoupledL2Base(implicit p: Parameters) extends LazyModule with Has
       case EdgeOutKey => node.out.head._2
       case BankBitsKey => bankBits
     })))
-    topDown.foreach { t =>
-      for ((s, i) <- slices.zipWithIndex) {
-        t.io.msStatus(i) := s.io.msStatus.get
-        t.io.msAlloc(i) := s.io.msAlloc.get
-        t.io.dirResult(i) := s.io.dirResult.get
-        t.io.hitPfInMSHR(i) := s.io.hitPfInMSHR.get
-        t.io.pfLateInMSHR(i) := s.io.pfLateInMSHR.get
-        t.io.pfSent(i) := s.io.pfSent.get
-      }
-      t.io.debugTopDown <> io.debugTopDown
-    }
-    when (topDown.isEmpty.B) {
-      io.debugTopDown.l2MissMatch := false.B
+    topDown match {
+      case Some(t) =>
+        for ((s, i) <- slices.zipWithIndex) {
+          t.io.msStatus(i) := s.io.msStatus.get
+          t.io.msAlloc(i) := s.io.msAlloc.get
+          t.io.dirResult(i) := s.io.dirResult.get
+          t.io.hitPfInMSHR(i) := s.io.hitPfInMSHR.get
+          t.io.pfLateInMSHR(i) := s.io.pfLateInMSHR.get
+          t.io.pfSent(i) := s.io.pfSent.get
+        }
+        t.io.debugTopDown <> io.debugTopDown
+      case None => io.debugTopDown.l2MissMatch := false.B
     }
 
     io.l2Miss := RegNext(slices.map(_.io.l2Miss).reduce(_ || _))