timing(TL2CHICoupledL2): 2-stage cap P-Credit Queue (OpenXiangShan#449)

Author: Kumonda221-CrO3

src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala

@@ -160,6 +160,11 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
         // PCredit queue
         class EmptyBundle extends Bundle
 
+        class PCrdGranted extends Bundle {
+          val pCrdType = UInt(PCRDTYPE_WIDTH.W)
+          val srcID = UInt(SRCID_WIDTH.W)
+        }
+
         val (mmioQuerys, mmioGrants) = mmio.io_pCrd.map { case x => (x.query, x.grant) }.unzip
         val (slicesQuerys, slicesGrants) = slices.map { case s =>
           (s.io_pCrd.map(_.query), s.io_pCrd.map(_.grant))
@@ -169,13 +174,13 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
 
         val mshrEntryCount = mshrPCrdQuerys.length
 
-        val pCrdQueue = Module(new Queue(new Bundle {
-          val pCrdType = UInt(PCRDTYPE_WIDTH.W)
-          val srcID = UInt(SRCID_WIDTH.W)
-        }, entries = mshrEntryCount))
+        val pCrdQueue_s2 = Module(new Queue(new PCrdGranted, entries = mshrEntryCount - 2))
+        val pCrdQueue_s3 = Module(new Queue(new PCrdGranted, entries = 2))
+
+        pCrdQueue_s3.io.enq <> pCrdQueue_s2.io.deq
 
         // PCredit hit by MSHRs
-        val mshrPCrdHits = mshrPCrdQuerys.map((_, pCrdQueue.io.deq)).map { case (q, h) => {
+        val mshrPCrdHits = mshrPCrdQuerys.map((_, pCrdQueue_s3.io.deq)).map { case (q, h) => {
           q.valid && h.valid && q.bits.pCrdType === h.bits.pCrdType && q.bits.srcID === h.bits.srcID
         }}
 
@@ -191,7 +196,7 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
         val mshrPCrdArbOut = {
           val arbPort = Wire(Decoupled(new EmptyBundle))
           arbPort.ready := true.B
-          pCrdQueue.io.deq.ready := arbPort.valid
+          pCrdQueue_s3.io.deq.ready := arbPort.valid
           arbPort
         }
 
@@ -204,12 +209,12 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
         val pCrdGrantType_s1 = RegNext(rxrsp.bits.pCrdType)
         val pCrdGrantSrcID_s1 = RegNext(rxrsp.bits.srcID)
 
-        pCrdQueue.io.enq.valid := pCrdGrantValid_s1
-        pCrdQueue.io.enq.bits.pCrdType := pCrdGrantType_s1
-        pCrdQueue.io.enq.bits.srcID := pCrdGrantSrcID_s1
+        pCrdQueue_s2.io.enq.valid := pCrdGrantValid_s1
+        pCrdQueue_s2.io.enq.bits.pCrdType := pCrdGrantType_s1
+        pCrdQueue_s2.io.enq.bits.srcID := pCrdGrantSrcID_s1
 
         val grantCnt = RegInit(0.U(64.W))
-        when (pCrdQueue.io.deq.ready) {
+        when (pCrdQueue_s3.io.deq.ready) {
           grantCnt := grantCnt + 1.U
         }
         dontTouch(grantCnt)
@@ -266,7 +271,7 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
         /**
           * performance counters
           */
-        XSPerfAccumulate("pcrd_count", pCrdQueue.io.enq.fire)
+        XSPerfAccumulate("pcrd_count", pCrdQueue_s2.io.enq.fire)
     }
   }