refactor(priv): totally abandon rtl_sys_slow_path

In previous commit e6b9212, amo and system instructions were changed to use slow path handler, in order to reduce the number of instruction entries in the execute() function, which improved the performance of NEMU.

As the number of RISC-V instructions develops, RVV, RVB, RVK introducing a large number of new instruction. In this context, using slow path handler no longer brings significant performance gains, and the complex decoding and execution logic reduces code readability and maintainability.

Testing shows that:
* When PERF_OPT enabled, the execution time of linux-hello and xvisor-hello increases by 0.68%;
* When PERF_OPT disabled, the execution time of linux-hello decreases by 0.8%

Author: cebarobot

src/cpu/cpu-exec.c

@@ -123,7 +123,7 @@ uint64_t get_abs_instr_count() {
 uint64_t get_abs_instr_count_csr() {
 #if defined(CONFIG_INSTR_CNT_BY_BB)
   return get_abs_instr_count() + prev_s->idx_in_bb - 1;
-  // s of this instruction is saved into prev_s, before csrrw() in rtl_sys_slow_path().
+  // s of this instruction is saved into prev_s, in EHelper of csrrw/csrrs/csrrc.
 #elif defined(CONFIG_INSTR_CNT_BY_INSTR)
   // INSTR-level
   return g_nr_guest_instr;
@@ -478,7 +478,7 @@ static void execute(int n) {
 end_of_loop:
   // Here is per loop action and some priv instruction action.
   // If end_of_bb and n_remain <= 0, it will goto here.
-  // Most of priv instruction (using rtl_sys_slow_path()) will goto here.
+  // Most of priv instruction (using rtl_priv_jr() or rtl_priv_next()) will goto here.
 
   // Settle instruction counting for the last instruction:
   // - If it is end_of_bb and n_remain < 0, it will goto here without "per inst action".

src/isa/riscv64/include/isa-all-instr.h

@@ -40,64 +40,83 @@
 #define AMO_INSTR_TERNARY(f) f(atomic)
 #endif
 
-#ifdef CONFIG_RVH
-#ifdef CONFIG_RV_SVINVAL
-  #define RVH_INST_BINARY(f) f(hfence_vvma) f(hfence_gvma) f(hinval_vvma) f(hinval_gvma) \
-    f(hlv_b) f(hlv_bu) f(hlv_h) f(hlv_hu) f(hlvx_hu) f(hlv_w) f(hlvx_wu) f(hlv_wu) f(hlv_d) \
-    f(hsv_b) f(hsv_h) f(hsv_w) f(hsv_d)
-#else
-  #define RVH_INST_BINARY(f) f(hfence_vvma) f(hfence_gvma) \
-    f(hlv_b) f(hlv_bu) f(hlv_h) f(hlv_hu) f(hlvx_hu) f(hlv_w) f(hlvx_wu) f(hlv_wu) f(hlv_d) \
-    f(hsv_b) f(hsv_h) f(hsv_w) f(hsv_d)
-#endif // CONFIG_RV_SVINVAL
-#else
-  #define RVH_INST_BINARY(f)
-#endif // CONFIG_RVH
+#ifdef CONFIG_RV_ZAWRS
+  #define ZAWRS_INSTR_NULLARY(f) \
+    f(wrs_nto) f(wrs_sto)
+#else // CONFIG_RV_ZAWRS
+  #define ZAWRS_INSTR_NULLARY(f)
+#endif // CONFIG_RV_ZAWRS
+
+/********************** SYS INSTR NULLARY **********************/
 
-#if defined(CONFIG_DEBUG) || defined(CONFIG_SHARE)
 #ifdef CONFIG_RV_SMRNMI
-#define SYS_NMI_NULLARY(f) \
-  f(mnret)
-#else
-#define SYS_NMI_NULLARY(f)
-#endif
-#ifdef CONFIG_RV_ZAWRS
-#define SYS_ZAWRS_NULLARY(f) \
-  f(wrs_nto) f(wrs_sto)
-#else
-#define SYS_ZAWRS_NULLARY(f)
-#endif
+  #define SYS_SMRNMI_INSTR_NULLARY(f) \
+    f(mnret)
+#else // CONFIG_RV_SMRNMI
+  #define SYS_SMRNMI_INSTR_NULLARY(f)
+#endif // CONFIG_RV_SMRNMI
+
 #ifdef CONFIG_RV_SVINVAL
+  #define SYS_SVINVAL_INSTR_NULLARY(f) \
+    f(sfence_w_inval) f(sfence_inval_ir)
+#else // CONFIG_RV_SVINVAL
+  #define SYS_SVINVAL_INSTR_NULLARY(f)
+#endif // CONFIG_RV_SVINVAL
+
 #define SYS_INSTR_NULLARY(f) \
   f(ecall) f(ebreak) f(c_ebreak) f(mret) f(sret) f(wfi) \
-  SYS_ZAWRS_NULLARY(f) \
-  f(sfence_w_inval) f(sfence_inval_ir)
-#define SYS_INSTR_BINARY(f) \
-  f(sfence_vma) f(sinval_vma) RVH_INST_BINARY(f)
-#else
-#define SYS_INSTR_NULLARY(f) \
-  f(ecall) f(ebreak) f(c_ebreak) f(mret) f(sret) f(wfi) \
-  SYS_ZAWRS_NULLARY(f)
+  SYS_SMRNMI_INSTR_NULLARY(f) \
+  SYS_SVINVAL_INSTR_NULLARY(f)
+
+/********************** SYS INSTR BINARY (2 op) **********************/
+
+#ifdef CONFIG_RVH
+  #define SYS_RVH_INSTR_BINARY(f) \
+    f(hlv_b) f(hlv_bu) f(hlv_h) f(hlv_hu) f(hlv_w) f(hlv_wu) f(hlv_d) \
+    f(hlvx_hu) f(hlvx_wu) \
+    f(hsv_b) f(hsv_h) f(hsv_w) f(hsv_d)
+#else // CONFIG_RVH
+  #define SYS_RVH_INSTR_BINARY(f)
+#endif // CONFIG_RVH
+
 #define SYS_INSTR_BINARY(f) \
-  f(sfence_vma) RVH_INST_BINARY(f)
-#endif
+  SYS_RVH_INSTR_BINARY(f)
+
+/********************** SYS INSTR TERNARY (3 op) **********************/
+
+// Instructions sfence.vma / hfence.vvma / hfence.gvma have 2 operands (rs1, rs2),
+// But NEMU's print_asm_template2 is for (rd, rs1). We have to treat them as 3 operands.
+
+#ifdef CONFIG_RV_SVINVAL
+  #define SYS_SVINVAL_INSTR_TERNARY(f) \
+    f(sinval_vma)
+  #define SYS_SVINVAL_RVH_INSTR_TERNARY(f) \
+    f(hinval_vvma) f(hinval_gvma)
+#else // CONFIG_RV_SVINVAL
+  #define SYS_SVINVAL_INSTR_TERNARY(f)
+  #define SYS_SVINVAL_RVH_INSTR_TERNARY(f)
+#endif // CONFIG_RV_SVINVAL
 
-#define SYS_INSTR_TERNARY(f) \
-  f(csrrw) f(csrrs) f(csrrc) f(csrrwi) f(csrrsi) f(csrrci)
-#else
 #ifdef CONFIG_RVH
-#define SYS_NMI_NULLARY(f)
-#define SYS_INSTR_NULLARY(f) f(c_ebreak)
-#define SYS_INSTR_BINARY(f)
-#define SYS_INSTR_TERNARY(f) f(priv) f(hload) f(hstore)
-#else
-#define SYS_NMI_NULLARY(f)
-#define SYS_INSTR_NULLARY(f) f(c_ebreak)
-#define SYS_INSTR_BINARY(f)
-#define SYS_INSTR_TERNARY(f) f(system)
+  #define SYS_RVH_INSTR_TERNARY(f) \
+    f(hfence_vvma) f(hfence_gvma) \
+    SYS_SVINVAL_RVH_INSTR_TERNARY(f)
+#else // CONFIG_RVH
+  #define SYS_RVH_INSTR_TERNARY(f)
 #endif // CONFIG_RVH
-#endif
-// TODO: sfence.vma and sinval.vma need two reg operand, only one(addr) now
+
+#define SYS_INSTR_TERNARY(f) \
+  f(sfence_vma) \
+  SYS_SVINVAL_INSTR_TERNARY(f) \
+  SYS_RVH_INSTR_TERNARY(f)
+
+
+/********************** SYS INSTR TERNARY CSR (csr) **********************/
+
+#define SYS_INSTR_TERNARY_CSR(f) \
+  f(csrrw) f(csrrs) f(csrrc) \
+  f(csrrwi) f(csrrsi) f(csrrci)
+
 
 #ifdef CONFIG_RVV
 #define VECTOR_INSTR_TERNARY(f) \
@@ -280,15 +299,13 @@
 #endif // CONFIG_FPU_NONE
 
 #ifdef CONFIG_RV_ZIMOP
-#define ZIMOP_INSTR_BINARY(f) \
-  f(mop_r_n)
-
-#define ZIMOP_INSTR_TERNARY(f) \
-  f(mop_rr_n)
-
+  #define ZIMOP_INSTR_BINARY(f) \
+    f(mop_r_n)
+  #define ZIMOP_INSTR_TERNARY(f) \
+    f(mop_rr_n)
 #else
-#define ZIMOP_INSTR_BINARY(f)
-#define ZIMOP_INSTR_TERNARY(f)
+  #define ZIMOP_INSTR_BINARY(f)
+  #define ZIMOP_INSTR_TERNARY(f)
 #endif // CONFIG_RV_ZIMOP
 
 #ifdef CONFIG_RV_ZCMOP
@@ -320,8 +337,8 @@
   ZIHINTPAUSE_INSTR_NULLARY(f) \
   f(fence_i) f(fence) \
   SYS_INSTR_NULLARY(f)   \
-  SYS_NMI_NULLARY(f) \
   f(p_ret) \
+  ZAWRS_INSTR_NULLARY(f) \
   ZCMOP_INSTR_NULLARY(f)
 
 #define INSTR_UNARY(f) \
@@ -360,6 +377,7 @@
   f(p_inc) f(p_dec) \
   AMO_INSTR_TERNARY(f) \
   AMO_CAS_INSTR(f) \
+  SYS_INSTR_TERNARY(f) \
   FLOAT_INSTR_TERNARY(f) \
   BITMANIP_INSTR_TERNARY(f) \
   CRYPTO_INSTR_TERNARY(f) \
@@ -373,7 +391,7 @@
   ZCB_INSTR_TERNARY(f)
 
 #define INSTR_TERNARY_CSR(f) \
-  SYS_INSTR_TERNARY(f) 
+  SYS_INSTR_TERNARY_CSR(f) 
 
 def_all_EXEC_ID();
 

src/isa/riscv64/instr/decode.c

@@ -141,30 +141,9 @@ int isa_fetch_decode(Decode *s) {
 
     case EXEC_ID_p_ret: case EXEC_ID_c_jr: case EXEC_ID_c_jalr: case EXEC_ID_jalr:
     case EXEC_ID_c_ebreak:
-#if defined(CONFIG_DEBUG) || defined(CONFIG_SHARE)
     case EXEC_ID_mret: case EXEC_ID_sret: case EXEC_ID_ecall: case EXEC_ID_ebreak:
     IFDEF(CONFIG_RV_SMRNMI, case EXEC_ID_mnret:)
-#endif
       s->type = INSTR_TYPE_I; break;
-
-#if !defined(CONFIG_DEBUG) && !defined(CONFIG_SHARE)
-#ifdef CONFIG_RVH
-    case EXEC_ID_priv:
-#else // CONFIG_RVH
-    case EXEC_ID_system:
-#endif // CONFIG_RVH
-      if (s->isa.instr.i.funct3 == 0) {
-        switch (s->isa.instr.csr.csr) {
-          case 0x0:   // ecall
-          case 0x1:   // ebreak
-          case 0x102: // sret
-          case 0x302: // mret
-          IFDEF(CONFIG_RV_SMRNMI, case 0x702: )// mnret
-            s->type = INSTR_TYPE_I;
-        }
-      }
-      break;
-#endif // CONFIG_DEBUG
   }
 
   return idx;