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| 1 | +/** ************************************************************************************* |
| 2 | + * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences |
| 3 | + * Copyright (c) 2020-2021 Peng Cheng Laboratory |
| 4 | + * |
| 5 | + * XiangShan is licensed under Mulan PSL v2. |
| 6 | + * You can use this software according to the terms and conditions of the Mulan PSL v2. |
| 7 | + * You may obtain a copy of Mulan PSL v2 at: |
| 8 | + * http://license.coscl.org.cn/MulanPSL2 |
| 9 | + * |
| 10 | + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, |
| 11 | + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, |
| 12 | + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. |
| 13 | + * |
| 14 | + * See the Mulan PSL v2 for more details. |
| 15 | + * ************************************************************************************* |
| 16 | + */ |
| 17 | + |
| 18 | +package openLLC |
| 19 | + |
| 20 | +import chisel3._ |
| 21 | +import chisel3.util._ |
| 22 | +import org.chipsalliance.cde.config.Parameters |
| 23 | +import coupledL2.tl2chi._ |
| 24 | +import utility.{FastArbiter} |
| 25 | + |
| 26 | +class MMIODiverger(implicit p: Parameters) extends LLCModule with HasCHIOpcodes { |
| 27 | + val io = IO(new Bundle() { |
| 28 | + val in = Vec(numRNs, Flipped(new DecoupledPortIO())) |
| 29 | + val out = new Bundle() { |
| 30 | + val cache = Vec(numRNs, new DecoupledPortIO()) |
| 31 | + val uncache = new DecoupledNoSnpPortIO() |
| 32 | + } |
| 33 | + }) |
| 34 | + |
| 35 | + def reqFromMMIO(req: CHIREQ): Bool = req.txnID(TXNID_WIDTH - 1) |
| 36 | + def datFromMMIO(dat: CHIDAT): Bool = dat.opcode === NonCopyBackWrData |
| 37 | + |
| 38 | + val mmioReqArb = Module(new FastArbiter(new CHIREQ(), numRNs)) |
| 39 | + val mmioDatArb = Module(new FastArbiter(new CHIDAT(), numRNs)) |
| 40 | + val receiptQueue = Module(new Queue(new CHIRSP(), entries = numRNs, pipe = true, flow = true)) |
| 41 | + |
| 42 | + receiptQueue.io.enq.valid := io.out.uncache.tx.req.fire && io.out.uncache.tx.req.bits.opcode === ReadNoSnp |
| 43 | + receiptQueue.io.enq.bits := { |
| 44 | + val receipt = WireInit(0.U.asTypeOf(new CHIRSP())) |
| 45 | + receipt.opcode := ReadReceipt |
| 46 | + receipt.txnID := io.out.uncache.tx.req.bits.txnID |
| 47 | + receipt.tgtID := io.out.uncache.tx.req.bits.srcID |
| 48 | + receipt |
| 49 | + } |
| 50 | + receiptQueue.io.deq.ready := Cat(io.in.zipWithIndex.map { case (in, i) => |
| 51 | + in.rx.rsp.ready && receiptQueue.io.deq.bits.tgtID === i.U |
| 52 | + }).orR |
| 53 | + |
| 54 | + mmioReqArb.io.in.zip(io.in.map(_.tx.req)).foreach { case (in, e) => |
| 55 | + in.valid := e.valid && reqFromMMIO(e.bits) |
| 56 | + in.bits := e.bits |
| 57 | + } |
| 58 | + mmioReqArb.io.out.ready := io.out.uncache.tx.req.ready |
| 59 | + |
| 60 | + mmioDatArb.io.in.zip(io.in.map(_.tx.dat)).foreach { case (in, e) => |
| 61 | + in.valid := e.valid && datFromMMIO(e.bits) |
| 62 | + in.bits := e.bits |
| 63 | + } |
| 64 | + mmioDatArb.io.out.ready := io.out.uncache.tx.dat.ready |
| 65 | + |
| 66 | + io.in.zip(io.out.cache).zipWithIndex.foreach { case ((in, out), i) => |
| 67 | + out.tx.req.valid := in.tx.req.valid && !reqFromMMIO(in.tx.req.bits) |
| 68 | + out.tx.req.bits := in.tx.req.bits |
| 69 | + out.tx.dat.valid := in.tx.dat.valid && !datFromMMIO(in.tx.dat.bits) |
| 70 | + out.tx.dat.bits := in.tx.dat.bits |
| 71 | + out.tx.rsp <> in.tx.rsp |
| 72 | + |
| 73 | + out.rx.rsp.ready := in.rx.rsp.ready && (!receiptQueue.io.deq.valid || receiptQueue.io.deq.bits.tgtID =/= i.U) && |
| 74 | + (!io.out.uncache.rx.rsp.valid || io.out.uncache.rx.rsp.bits.tgtID =/= i.U) |
| 75 | + out.rx.dat.ready := in.rx.dat.ready && (!io.out.uncache.rx.dat.valid || io.out.uncache.rx.dat.bits.tgtID =/= i.U) |
| 76 | + |
| 77 | + in.tx.req.ready := io.out.uncache.tx.req.fire && mmioReqArb.io.chosen === i.U || out.tx.req.fire |
| 78 | + in.tx.dat.ready := io.out.uncache.tx.dat.fire && mmioDatArb.io.chosen === i.U || out.tx.dat.fire |
| 79 | + |
| 80 | + in.rx.rsp.valid := out.rx.rsp.valid || io.out.uncache.rx.rsp.valid && io.out.uncache.rx.rsp.bits.tgtID === i.U || |
| 81 | + receiptQueue.io.deq.valid && receiptQueue.io.deq.bits.tgtID === i.U |
| 82 | + in.rx.rsp.bits := Mux( |
| 83 | + receiptQueue.io.deq.valid && receiptQueue.io.deq.bits.tgtID === i.U, |
| 84 | + receiptQueue.io.deq.bits, |
| 85 | + Mux( |
| 86 | + io.out.uncache.rx.rsp.valid && io.out.uncache.rx.rsp.bits.tgtID === i.U, |
| 87 | + io.out.uncache.rx.rsp.bits, |
| 88 | + out.rx.rsp.bits |
| 89 | + ) |
| 90 | + ) |
| 91 | + in.rx.dat.valid := out.rx.dat.valid || io.out.uncache.rx.dat.valid && io.out.uncache.rx.dat.bits.tgtID === i.U |
| 92 | + in.rx.dat.bits := Mux( |
| 93 | + io.out.uncache.rx.dat.valid && io.out.uncache.rx.dat.bits.tgtID === i.U, |
| 94 | + io.out.uncache.rx.dat.bits, |
| 95 | + out.rx.dat.bits |
| 96 | + ) |
| 97 | + in.rx.snp <> out.rx.snp |
| 98 | + } |
| 99 | + |
| 100 | + io.out.uncache.tx.req.valid := mmioReqArb.io.out.valid && receiptQueue.io.enq.ready |
| 101 | + io.out.uncache.tx.req.bits := mmioReqArb.io.out.bits |
| 102 | + io.out.uncache.tx.req.bits.order := OrderEncodings.None |
| 103 | + io.out.uncache.tx.dat.valid := mmioDatArb.io.out.valid |
| 104 | + io.out.uncache.tx.dat.bits := mmioDatArb.io.out.bits |
| 105 | + |
| 106 | + io.out.uncache.rx.rsp.ready := Cat(io.in.zipWithIndex.map { case (in, i) => |
| 107 | + in.rx.rsp.ready && io.out.uncache.rx.rsp.bits.tgtID === i.U && |
| 108 | + (!receiptQueue.io.deq.valid || receiptQueue.io.deq.bits.tgtID =/= i.U) |
| 109 | + }).orR |
| 110 | + io.out.uncache.rx.dat.ready := Cat(io.in.zipWithIndex.map { case (in, i) => |
| 111 | + in.rx.dat.ready && io.out.uncache.rx.dat.bits.tgtID === i.U }).orR |
| 112 | +} |
| 113 | + |
| 114 | +class MMIOMerger(implicit p: Parameters) extends LLCModule { |
| 115 | + val io = IO(new Bundle() { |
| 116 | + val in = new Bundle() { |
| 117 | + val cache = Flipped(new DecoupledNoSnpPortIO()) |
| 118 | + val uncache = Flipped(new DecoupledNoSnpPortIO()) |
| 119 | + } |
| 120 | + val out = new DecoupledNoSnpPortIO() |
| 121 | + }) |
| 122 | + |
| 123 | + val in = io.in |
| 124 | + val out = io.out |
| 125 | + |
| 126 | + def datToMMIO(dat: CHIDAT): Bool = dat.txnID(TXNID_WIDTH - 1) |
| 127 | + def rspToMMIO(rsp: CHIRSP): Bool = rsp.txnID(TXNID_WIDTH - 1) |
| 128 | + |
| 129 | + out.tx.req.valid := in.cache.tx.req.valid || in.uncache.tx.req.valid |
| 130 | + out.tx.req.bits := Mux(in.uncache.tx.req.valid, in.uncache.tx.req.bits, in.cache.tx.req.bits) |
| 131 | + out.tx.dat.valid := in.cache.tx.dat.valid || in.uncache.tx.dat.valid |
| 132 | + out.tx.dat.bits := Mux(in.uncache.tx.dat.valid, in.uncache.tx.dat.bits, in.cache.tx.dat.bits) |
| 133 | + out.rx.rsp.ready := in.cache.rx.rsp.fire || in.uncache.rx.rsp.fire |
| 134 | + out.rx.dat.ready := in.cache.rx.dat.fire || in.uncache.rx.dat.fire |
| 135 | + in.cache.tx.req.ready := out.tx.req.ready && !in.uncache.tx.req.valid |
| 136 | + in.cache.tx.dat.ready := out.tx.dat.ready && !in.uncache.tx.dat.valid |
| 137 | + in.cache.rx.dat.valid := out.rx.dat.valid && !datToMMIO(out.rx.dat.bits) |
| 138 | + in.cache.rx.dat.bits := out.rx.dat.bits |
| 139 | + in.cache.rx.rsp.valid := out.rx.rsp.valid && !rspToMMIO(out.rx.rsp.bits) |
| 140 | + in.cache.rx.rsp.bits := out.rx.rsp.bits |
| 141 | + |
| 142 | + in.uncache.tx.req.ready := out.tx.req.ready |
| 143 | + in.uncache.tx.dat.ready := out.tx.dat.ready |
| 144 | + in.uncache.rx.dat.valid := out.rx.dat.valid && datToMMIO(out.rx.dat.bits) |
| 145 | + in.uncache.rx.dat.bits := out.rx.dat.bits |
| 146 | + in.uncache.rx.rsp.valid := out.rx.rsp.valid && rspToMMIO(out.rx.rsp.bits) |
| 147 | + in.uncache.rx.rsp.bits := out.rx.rsp.bits |
| 148 | +} |
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