feat(MainPipe, ResponseUnit): support WriteEvictOrEvict transaction (#30)

Author: sumailyyc

src/main/scala/openLLC/MainPipe.scala

@@ -126,9 +126,11 @@ class MainPipe(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
   val cleanInvalid_s3       = !refill_task_s3 && opcode_s3 === CleanInvalid
   val cleanShared_s3        = !refill_task_s3 && opcode_s3 === CleanShared
   val writeCleanFull_s3     = !refill_task_s3 && opcode_s3 === WriteCleanFull
+  val writeEvictOrEvict_s3  = !refill_task_s3 && opcode_s3 === WriteEvictOrEvict && afterIssueE.B
 
-  assert(!task_s3.valid || refill_task_s3 || readNotSharedDirty_s3 || readUnique_s3 || makeUnique_s3 || writeBackFull_s3 ||
-    evict_s3 || makeInvalid_s3 || cleanInvalid_s3 || cleanShared_s3 || writeCleanFull_s3, "Unsupported opcode")
+  assert(!task_s3.valid || refill_task_s3 ||
+    readNotSharedDirty_s3 || readUnique_s3 || makeUnique_s3 || writeBackFull_s3 || evict_s3 || makeInvalid_s3 ||
+    cleanInvalid_s3 || cleanShared_s3 || writeCleanFull_s3 || writeEvictOrEvict_s3, "Unsupported opcode")
 
   /**
     * Requests have different coherence states after processing
@@ -140,7 +142,7 @@ class MainPipe(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
     */
   val exclusiveReq_s3 = readUnique_s3 || readNotSharedDirty_s3 && !peerRNs_hit_s3 || makeUnique_s3
   val sharedReq_s3    = readNotSharedDirty_s3 && peerRNs_hit_s3
-  val releaseReq_s3   = writeBackFull_s3 || evict_s3
+  val releaseReq_s3   = writeBackFull_s3 || evict_s3 || writeEvictOrEvict_s3
   val invalidReq_s3   = makeInvalid_s3 || cleanInvalid_s3
   val cleanReq_s3     = cleanInvalid_s3 || cleanShared_s3
 
@@ -257,6 +259,8 @@ class MainPipe(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
   val cleanInvalid_s4       = RegNext(cleanInvalid_s3, false.B)
   val cleanShared_s4        = RegNext(cleanShared_s3, false.B)
   val writeCleanFull_s4     = RegNext(writeCleanFull_s3, false.B)
+  val writeEvictOrEvict_s4  = RegNext(writeEvictOrEvict_s3, false.B)
+
   val sharedReq_s4          = RegNext(sharedReq_s3, false.B)
   val exclusiveReq_s4       = RegNext(exclusiveReq_s3, false.B)
   val releaseReq_s4         = RegNext(releaseReq_s3, false.B)
@@ -355,7 +359,7 @@ class MainPipe(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
     ).asBools
   )
   refill_s4.valid := task_s4.valid && (
-    (sharedReq_s4 || writeBackFull_s4) && !self_hit_s4 ||
+    (sharedReq_s4 || writeBackFull_s4 || writeEvictOrEvict_s4) && !self_hit_s4 ||
     replace_snoop_s4
   )
   refill_s4.bits.state.s_refill := false.B
@@ -401,10 +405,11 @@ class MainPipe(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
   comp_s4.bits.state.s_urgentRead := true.B
   comp_s4.bits.state.w_datRsp := !(readNotSharedDirty_s4 || readUnique_s4)
   comp_s4.bits.state.w_snpRsp := !Cat(snpVec_comp_s4).orR
-  comp_s4.bits.state.w_compack := !(readUnique_s4 || readNotSharedDirty_s4 || makeUnique_s4)
+  comp_s4.bits.state.w_compack := !(readUnique_s4 || readNotSharedDirty_s4 || makeUnique_s4 ||
+    writeEvictOrEvict_s4 && self_hit_s4)
   comp_s4.bits.state.w_comp := !(cleanReq_s4 && self_hit_s4 && selfDirty_s4)
   comp_s4.bits.task := comp_task_s4
-  comp_s4.bits.is_miss := (readNotSharedDirty_s4 || readUnique_s4) && !self_hit_s4
+  comp_s4.bits.is_miss := !self_hit_s4
 
   /**  Read/Write request to MemUnit **/
   val mem_task_s4 = WireInit(req_s4)

src/main/scala/openLLC/RefillUnit.scala

@@ -30,7 +30,7 @@ class RefillBufRead(implicit p: Parameters) extends LLCBundle {
 
 class RefillState(implicit p: Parameters) extends LLCBundle {
   val s_refill = Bool()
-  val w_datRsp   = Bool()
+  val w_datRsp = Bool()
   val w_snpRsp = Bool()
 }
 
@@ -99,13 +99,14 @@ class RefillUnit(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
     when(canUpdate) {
       val entry = buffer(update_id)
       val isWriteBackFull = entry.task.chiOpcode === WriteBackFull
+      val isWriteEvictOrEvict = entry.task.chiOpcode === WriteEvictOrEvict
       val inv_CBWrData = rspData.bits.resp === I
       val cancel = isWriteBackFull && inv_CBWrData
       val clients_hit = entry.dirResult.clients.hit
       val clients_meta = entry.dirResult.clients.meta
 
       assert(
-        !isWriteBackFull || inv_CBWrData || clients_hit && clients_meta(rspData.bits.srcID).valid,
+        !isWriteBackFull && !isWriteEvictOrEvict || inv_CBWrData || clients_hit && clients_meta(rspData.bits.srcID).valid,
         "Non-exist block release?(addr: 0x%x)",
         Cat(entry.task.tag, entry.task.set, entry.task.bank, entry.task.off)
       )

src/main/scala/openLLC/ResponseUnit.scala

@@ -294,7 +294,8 @@ class ResponseUnit(implicit p: Parameters) extends LLCModule with HasCHIOpcodes
   txrsp.valid := txrspArb.io.out.valid
   txrsp.bits := txrspArb.io.out.bits
   txrsp.bits.chiOpcode := Mux(
-    txrspArb.io.out.bits.chiOpcode === WriteBackFull || txrspArb.io.out.bits.chiOpcode === WriteCleanFull,
+    txrspArb.io.out.bits.chiOpcode === WriteBackFull || txrspArb.io.out.bits.chiOpcode === WriteCleanFull ||
+    txrspArb.io.out.bits.chiOpcode === WriteEvictOrEvict && buffer(txrspArb.io.chosen).is_miss,
     CompDBIDResp,
     Comp
   )

src/main/scala/openLLC/TopDownMonitor.scala

@@ -20,9 +20,10 @@ package openLLC
 import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
+import coupledL2.tl2chi._
 import utility.{XSPerfAccumulate}
 
-class TopDownMonitor()(implicit p: Parameters) extends LLCModule {
+class TopDownMonitor()(implicit p: Parameters) extends LLCModule with HasCHIOpcodes {
   val io = IO(new Bundle() {
     val msStatus = Vec(banks, Vec(mshrs.response, Flipped(ValidIO(new ResponseInfo()))))
     val debugTopDown = new Bundle() {
@@ -43,7 +44,7 @@ class TopDownMonitor()(implicit p: Parameters) extends LLCModule {
                               else Cat(ms.bits.tag, ms.bits.set, i.U(bankBits - 1, 0))
             val pBlockAddr  = (pAddr.bits >> 6.U).asUInt
 
-            val isMiss   = ms.valid && ms.bits.is_miss
+            val isMiss = ms.valid && ms.bits.is_miss && (ms.bits.opcode === ReadNotSharedDirty || ms.bits.opcode === ReadUnique)
             pAddr.valid && msBlockAddr === pBlockAddr && isMiss
         }
     }