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fix: mempool
1 parent 04ab600 commit 1e1ffdb

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5 files changed

+79
-3
lines changed

5 files changed

+79
-3
lines changed

src/main/scala/fpga/Host.scala

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ class Difftest2AXIs(val difftest_width: Int, val axis_width: Int) extends Module
6767
val rd_occupancy = wr_cnt_sync - rd_cnt // Calculate occupancy in read clock domain
6868

6969
val inTransfer = RegInit(false.B)
70+
val packetBeats = RegInit(VecInit(Seq.fill(axis_send_len)(0.U(axis_width.W))))
7071
val sendCnt = RegInit(0.U(log2Ceil(axis_send_len).W))
7172
val sendLast = sendCnt === (axis_send_len - 1).U
7273
val counter = RegInit(0.U(3.W)) // 0 to 7
@@ -86,6 +87,7 @@ class Difftest2AXIs(val difftest_width: Int, val axis_width: Int) extends Module
8687

8788
// Start transfer when we have data available
8889
when(loadNextPacket) {
90+
packetBeats := packetPayloadBeats
8991
rd_ptr := rd_ptr + 1.U
9092
rd_cnt := rd_cnt + 1.U // Increment read counter
9193
}
@@ -113,7 +115,7 @@ class Difftest2AXIs(val difftest_width: Int, val axis_width: Int) extends Module
113115

114116
// AXI output
115117
io.axis.valid := inTransfer
116-
io.axis.bits.data := packetPayloadBeats(sendCnt)
118+
io.axis.bits.data := packetBeats(sendCnt)
117119
io.axis.bits.last := inTransfer && sendLast && sendPacketEnd
118120
}
119121
}

src/test/csrc/fpga/xdma.cpp

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,11 @@ void FpgaXdma::start_transmit_thread() {
142142
}
143143

144144
void FpgaXdma::stop_thansmit_thread() {
145+
#ifdef FPGA_SIM
146+
for (int i = 0; i < CONFIG_DMA_CHANNELS; i++) {
147+
xdma_sim_interrupt(i);
148+
}
149+
#endif
145150
for (int i = 0; i < CONFIG_DMA_CHANNELS; i++) {
146151
if (receive_thread[i].joinable())
147152
receive_thread[i].join();
@@ -163,18 +168,50 @@ void FpgaXdma::read_xdma_thread(int channel) {
163168
size_t mem_get_idx = 0;
164169
while (running) {
165170
char *mem = xdma_mempool.get_free_chunk(&mem_get_idx);
171+
if (mem == nullptr) {
172+
continue;
173+
}
166174
#ifdef FPGA_SIM
167175
size_t size = xdma_sim_read(channel, mem, sizeof(FpgaPackgeHead));
168176
#else
169177
size_t size = read(xdma_c2h_fd[channel], mem, sizeof(FpgaPackgeHead));
170178
#endif // FPGA_SIM
179+
if (!running || size == 0) {
180+
break;
181+
}
171182
if (xdma_mempool.write_free_chunk(mem[0], mem_get_idx) == false) {
172183
printf("It should not be the case that no available block can be found\n");
173184
assert(0);
174185
}
175186
}
176187
}
177188

189+
void FpgaXdma::read_and_process_fallback() {
190+
printf("start channel 0\n");
191+
void *ptr = nullptr;
192+
int ret = posix_memalign(&ptr, 4096, sizeof(FpgaPackgeHead));
193+
if (ret != 0) {
194+
perror("posix_memalign failed");
195+
return;
196+
}
197+
FpgaPackgeHead *packge = (FpgaPackgeHead *)ptr;
198+
memset(packge, 0, sizeof(FpgaPackgeHead));
199+
while (running) {
200+
#ifdef FPGA_SIM
201+
size_t size = xdma_sim_read(0, (char *)packge, sizeof(FpgaPackgeHead));
202+
#else
203+
size_t size = read(xdma_c2h_fd[0], packge, sizeof(FpgaPackgeHead));
204+
#endif // FPGA_SIM
205+
if (!running || size == 0) {
206+
break;
207+
}
208+
for (size_t i = 0; i < DMA_PACKGE_NUM; i++) {
209+
v_difftest_Batch(packge->diff_packge[i].diff_packge);
210+
}
211+
}
212+
free(packge);
213+
}
214+
178215
void FpgaXdma::write_difftest_thread() {
179216
FpgaPackgeHead *packge;
180217
uint8_t recv_count = 0;

src/test/csrc/fpga/xdma.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,12 +77,16 @@ class FpgaXdma {
7777
}
7878
} else {
7979
#ifdef USE_THREAD_MEMPOOL
80+
#if defined(FPGA_SIM) && (CONFIG_DMA_CHANNELS == 1)
81+
read_and_process_fallback();
82+
#else
8083
std::unique_lock<std::mutex> lock(thread_mtx);
8184
start_transmit_thread();
8285
while (running) {
8386
thread_cv.wait(lock); // wait notify from stop
8487
}
8588
stop_thansmit_thread();
89+
#endif
8690
#else
8791
read_and_process();
8892
#endif // USE_THREAD_MEMPOOL
@@ -128,6 +132,7 @@ class FpgaXdma {
128132
void start_transmit_thread();
129133
void stop_thansmit_thread();
130134
void read_xdma_thread(int channel);
135+
void read_and_process_fallback();
131136
void write_difftest_thread();
132137
#else
133138
void read_and_process();

src/test/csrc/fpga_sim/xdma_sim.cpp

Lines changed: 33 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ typedef struct {
3131
pthread_mutex_t lock;
3232
pthread_cond_t read_cond;
3333
bool read_waiting;
34+
bool closed;
3435
int read_size;
3536
int write_size;
3637
char buffer[BUFFER_SIZE];
@@ -66,25 +67,45 @@ class xdma_sim {
6667
pthread_condattr_init(&cattr);
6768
pthread_condattr_setpshared(&cattr, PTHREAD_PROCESS_SHARED);
6869
pthread_cond_init(&shm_ptr->read_cond, &cattr);
70+
shm_ptr->closed = false;
6971
}
7072
}
7173
~xdma_sim() {
74+
interrupt();
7275
if (is_host) {
7376
shm_unlink(path);
7477
}
7578
munmap(shm_ptr, sizeof(xdma_shm));
7679
close(shm_fd);
7780
}
81+
void interrupt() {
82+
if (shm_ptr == nullptr) {
83+
return;
84+
}
85+
pthread_mutex_lock(&shm_ptr->lock);
86+
shm_ptr->closed = true;
87+
shm_ptr->read_waiting = false;
88+
pthread_cond_broadcast(&shm_ptr->read_cond);
89+
pthread_mutex_unlock(&shm_ptr->lock);
90+
}
7891
int read(char *buf, size_t size) {
7992
assert(size <= BUFFER_SIZE);
8093
pthread_mutex_lock(&shm_ptr->lock);
8194

95+
if (shm_ptr->closed) {
96+
pthread_mutex_unlock(&shm_ptr->lock);
97+
return 0;
98+
}
8299
shm_ptr->read_waiting = true;
83100
shm_ptr->write_size = 0;
84101
shm_ptr->read_size = size;
85-
while (shm_ptr->write_size < size) {
102+
while (shm_ptr->write_size < size && !shm_ptr->closed) {
86103
pthread_cond_wait(&shm_ptr->read_cond, &shm_ptr->lock);
87104
}
105+
if (shm_ptr->closed) {
106+
pthread_mutex_unlock(&shm_ptr->lock);
107+
return 0;
108+
}
88109
size_t to_copy = size < shm_ptr->write_size ? size : shm_ptr->write_size;
89110
memcpy(buf, shm_ptr->buffer, to_copy);
90111

@@ -94,10 +115,14 @@ class xdma_sim {
94115
}
95116
int write(const char *buf, unsigned char tlast, size_t size) {
96117
pthread_mutex_lock(&shm_ptr->lock);
97-
while (!shm_ptr->read_waiting) {
118+
while (!shm_ptr->read_waiting && !shm_ptr->closed) {
98119
pthread_mutex_unlock(&shm_ptr->lock);
99120
pthread_mutex_lock(&shm_ptr->lock);
100121
}
122+
if (shm_ptr->closed) {
123+
pthread_mutex_unlock(&shm_ptr->lock);
124+
return 0;
125+
}
101126
size_t space = shm_ptr->read_size - shm_ptr->write_size;
102127
size_t to_write = size < space ? size : space;
103128

@@ -128,6 +153,12 @@ void xdma_sim_close(int channel) {
128153
xsim[channel] = nullptr;
129154
}
130155

156+
void xdma_sim_interrupt(int channel) {
157+
if (xsim[channel] != nullptr) {
158+
xsim[channel]->interrupt();
159+
}
160+
}
161+
131162
int xdma_sim_read(int channel, char *buf, size_t size) {
132163
return xsim[channel]->read(buf, size);
133164
}

src/test/csrc/fpga_sim/xdma_sim.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020

2121
void xdma_sim_open(int channel, bool is_host);
2222
void xdma_sim_close(int channel);
23+
void xdma_sim_interrupt(int channel);
2324
int xdma_sim_read(int channel, char *buf, size_t size);
2425
int xdma_sim_write(int channel, const char *buf, uint8_t tlast, size_t size);
2526

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