FPGA: expose IO with finishFPGA

This change expose FPGA IO with finishFPGA, enabling us to wrap both
DUT, Difftest, and changing DiffTestBundle Interface within the same
wrapper. Only the output of Batch, with width declared at
DifftestMacros.v, will be exposed to FPGA.

Author: klin02

.github/workflows/main.yml

@@ -334,6 +334,6 @@ jobs:
       - name: FPGA-difftest Build
         run: |
             cd $NOOP_HOME
-            make sim-verilog MILL_ARGS="--difftest-config SF" -j2
+            make sim-verilog MILL_ARGS="--difftest-config ESBIDF" -j2
             cd ./difftest
             make fpga-build FPGA=1

src/main/scala/Difftest.scala

@@ -20,7 +20,7 @@ import chisel3._
 import chisel3.reflect.DataMirror
 import chisel3.util._
 import difftest.common.{DifftestWiring, FileControl}
-import difftest.gateway.{Gateway, GatewayConfig}
+import difftest.gateway.{FpgaDiffIO, Gateway, GatewayConfig, GatewayResult}
 import difftest.util.Profile
 
 import scala.annotation.tailrec
@@ -541,9 +541,8 @@ object DifftestModule {
 
   def get_current_interfaces(): Seq[(DifftestBundle, Int)] = interfaces.toSeq
 
-  def finish(cpu: String, createTopIO: Boolean): Option[DifftestTopIO] = {
+  def collect(cpu: String): GatewayResult = {
     val gateway = Gateway.collect()
-
     generateCppHeader(
       cpu,
       gateway.instances,
@@ -556,7 +555,19 @@ object DifftestModule {
     }
     generateVeriogHeader(gateway.vMacros)
     Profile.generateJson(cpu, interfaces.toSeq)
+    gateway
+  }
 
+  def finishFPGA(cpu: String): FpgaDiffIO = {
+    val gateway = collect(cpu)
+    val fpgaIO = gateway.fpgaIO.get
+    val io = IO(Output(chiselTypeOf(fpgaIO)))
+    io := fpgaIO
+    io
+  }
+
+  def finish(cpu: String, createTopIO: Boolean): Option[DifftestTopIO] = {
+    val gateway = collect(cpu)
     Option.when(createTopIO) {
       if (enabled) {
         createTopIOs(gateway.exit, gateway.step)

src/main/scala/Gateway.scala

@@ -103,11 +103,18 @@ case class GatewayConfig(
     if (isBatch) require(!hasDutZone)
     // Currently Delta depends on Batch to ensure update and sync order
     if (isDelta) require(isBatch)
+    // Batch provides unified IO interface for FPGA Diff
+    if (isFPGA) require(isBatch)
     // TODO: support dump and load together
     require(!(traceDump && traceLoad))
   }
 }
 
+class FpgaDiffIO(config: GatewayConfig) extends Bundle {
+  val data = UInt(config.batchBitWidth.W)
+  val enable = Bool()
+}
+
 case class GatewayResult(
   cppMacros: Seq[String] = Seq(),
   vMacros: Seq[String] = Seq(),
@@ -117,6 +124,7 @@ case class GatewayResult(
   cppExtModule: Option[Boolean] = None,
   exit: Option[UInt] = None,
   step: Option[UInt] = None,
+  fpgaIO: Option[FpgaDiffIO] = None,
 ) {
   def +(that: GatewayResult): GatewayResult = {
     GatewayResult(
@@ -128,6 +136,7 @@ case class GatewayResult(
       cppExtModule = if (cppExtModule.isDefined) cppExtModule else that.cppExtModule,
       exit = if (exit.isDefined) exit else that.exit,
       step = if (step.isDefined) step else that.step,
+      fpgaIO = if (fpgaIO.isDefined) fpgaIO else that.fpgaIO,
     )
   }
 }
@@ -199,6 +208,7 @@ object Gateway {
         structPacked = Some(config.isBatch),
         structAligned = Some(config.isDelta),
         step = Some(endpoint.step),
+        fpgaIO = endpoint.fpgaIO,
       )
     } else {
       GatewayResult(instances = instances) + GatewaySink.collect(config)
@@ -256,11 +266,16 @@ class GatewayEndpoint(instanceWithDelay: Seq[(DifftestBundle, Int)], config: Gat
   val step = IO(Output(UInt(config.stepWidth.W)))
   val control = Wire(new GatewaySinkControl(config))
 
+  val fpgaIO = Option.when(config.isFPGA)(IO(Output(new FpgaDiffIO(config))))
   if (config.isBatch) {
     val batch = Batch(toSink, config)
     step := RegNext(batch.step, 0.U) // expose Batch step to check timeout
     control.enable := batch.enable
     GatewaySink.batch(Batch.getTemplate, control, batch.io, config)
+    if (config.isFPGA) {
+      fpgaIO.get.data := batch.io.asUInt
+      fpgaIO.get.enable := batch.enable
+    }
   } else {
     val sink_enable = VecInit(toSink.map(_.valid).toSeq).asUInt.orR
     step := RegNext(sink_enable, 0.U)
@@ -292,17 +307,6 @@ object GatewaySink {
       case "dpic" => DPIC.batch(template, control, io, config)
       case _      => DPIC.batch(template, control, io, config) // Default: DPI-C
     }
-    val out = Option.when(config.isFPGA) {
-      IO(new Bundle {
-        val data = Output(UInt(config.batchBitWidth.W))
-        val enable = Output(Bool())
-      })
-    }
-    if (config.isFPGA) {
-      out.get.data := Cat(io.data, io.info)
-      out.get.enable := control.enable
-      dontTouch(out.get)
-    }
   }
 
   def collect(config: GatewayConfig): GatewayResult = {