riscv: Make mzero zero exact matrix register bytes

Emit exact-width stores in mzero so matrix register clearing never rounds up past the selected register size and clobbers adjacent storage.

Author: xyyy1420

target/riscv/insn_trans/trans_rvmm.c.inc

@@ -483,20 +483,29 @@ static bool trans_mzero(DisasContext *s, arg_mm_i *a)
         len = get_rows(s) * get_rows(s) * (s->cfg_ptr->melen / 8);
     }
 
-    /* tcg_gen_gvec_dup_imm encodes maxsz in SIMD_MAXSZ_BITS (8 bits, max
-     * 2040 bytes). Large matrix registers exceed this, so zero in chunks. */
-#define MZERO_GVEC_CHUNK 2040U
-    uint32_t total = ROUND_UP(len, 8);
     uint32_t base_ofs = mregs_ofs(s, a->md);
-    for (uint32_t off = 0; off < total; off += MZERO_GVEC_CHUNK) {
-        uint32_t this_len = MIN(total - off, MZERO_GVEC_CHUNK);
-        this_len = ROUND_UP(this_len, 8);
-        tcg_gen_gvec_dup_imm(MO_64, base_ofs + off, this_len, this_len, 0);
+    TCGv_i64 zero = tcg_constant_i64(0);
+    uint32_t off = 0;
+
+    while (len - off >= 8) {
+        tcg_gen_st_i64(zero, tcg_env, base_ofs + off);
+        off += 8;
+    }
+    if (len - off >= 4) {
+        tcg_gen_st32_i64(zero, tcg_env, base_ofs + off);
+        off += 4;
+    }
+    if (len - off >= 2) {
+        tcg_gen_st16_i64(zero, tcg_env, base_ofs + off);
+        off += 2;
+    }
+    if (len - off >= 1) {
+        tcg_gen_st8_i64(zero, tcg_env, base_ofs + off);
     }
-#undef MZERO_GVEC_CHUNK
     return true;
 }
 
+
 static bool trans_minit(DisasContext *s, arg_empty *a)
 {
     if (!require_matrix(s)) {