GenWithMstatush.scala

package vexriscv.demo

import vexriscv.plugin._
import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
import spinal.core._

/**
 * GenWithMstatush
 *
 * Demonstrates how to include the MstatushPlugin in a VexRiscv configuration.
 *
 * This configuration is based on GenSmallest but includes the MstatushPlugin
 * to implement the mstatush CSR (0x310), which represents the upper 32 bits
 * of the 64-bit mstatus register. In this RV32 implementation, mstatush is
 * hardwired to zero.
 *
 * To generate the Verilog:
 * {{{
 *   sbt "runMain vexriscv.demo.GenWithMstatush"
 * }}}
 */
object GenWithMstatush extends App{
  def cpu() = new VexRiscv(
    config = VexRiscvConfig(
      plugins = List(
        new IBusSimplePlugin(
          resetVector = 0x80000000l,
          cmdForkOnSecondStage = false,
          cmdForkPersistence = false,
          prediction = NONE,
          catchAccessFault = false,
          compressedGen = false
        ),
        new DBusSimplePlugin(
          catchAddressMisaligned = false,
          catchAccessFault = false
        ),
        new CsrPlugin(CsrPluginConfig.smallest),
        // MstatushPlugin adds mstatush CSR support
        // Set readOnly = false to allow writes (which have no effect)
        new MstatushPlugin(readOnly = true),
        new DecoderSimplePlugin(
          catchIllegalInstruction = false
        ),
        new RegFilePlugin(
          regFileReadyKind = plugin.SYNC,
          zeroBoot = false
        ),
        new IntAluPlugin,
        new SrcPlugin(
          separatedAddSub = false,
          executeInsertion = false
        ),
        new LightShifterPlugin,
        new HazardSimplePlugin(
          bypassExecute           = false,
          bypassMemory            = false,
          bypassWriteBack         = false,
          bypassWriteBackBuffer   = false,
          pessimisticUseSrc       = false,
          pessimisticWriteRegFile = false,
          pessimisticAddressMatch = false
        ),
        new BranchPlugin(
          earlyBranch = false,
          catchAddressMisaligned = false
        ),
        new YamlPlugin("cpu0.yaml")
      )
    )
  )

  SpinalVerilog(cpu())
}