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Building a Basic Template
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package corvus
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case class CorvusConfig() {
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// 在这里定义你的配置参数
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val numSCore: Int = 16
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val syncTreeFactor: Int = 4
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}
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package corvus
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import chisel3._
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import _root_.circt.stage.ChiselStage
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object Elaborate extends App {
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implicit private val p: CorvusConfig = CorvusConfig()
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ChiselStage.emitSystemVerilogFile(
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new Top,
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args,
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firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info", "-default-layer-specialization=enable")
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)
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}

src/main/scala/corvus/Top.scala

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package corvus
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import chisel3._
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import chisel3.util._
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class Top(implicit p:CorvusConfig) extends Module {
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val io = IO(new Bundle {
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val led = Output(UInt(8.W))
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})
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// 直接实例化SCore
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printf("CorvusTop: NUM_S_CORE = %d\n", p.numSCore.U)
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io.led := p.syncTreeFactor.U
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}

src/main/scala/gcd/DecoupledGCD.scala

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src/main/scala/gcd/GCD.scala

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