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wissyghYan-Yiming
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fix(TL2CHICoupledL2): modify signal io_cpu_halt to io_cpu_wfi (OpenXiangShan#482)
* In top, `io_cpu_halt` is misleading signal, as it may be mistaken for the debug command `halt`.
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CoupledL2/src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
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val io_chi = IO(new PortIO)
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val io_nodeID = IO(Input(UInt()))
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val io_cpu_halt = Option.when(cacheParams.enableL2Flush) (IO(Input(Bool())))
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val io_cpu_wfi = Option.when(cacheParams.enableL2Flush) (IO(Input(Bool())))
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// Check port width
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require(io_chi.tx.rsp.getWidth == io_chi.rx.rsp.getWidth);
@@ -265,7 +265,7 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
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linkMonitor.io.nodeID := io_nodeID
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/* exit coherency when: l2 flush of all slices is done and core is in WFI state */
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linkMonitor.io.exitco.foreach { _ :=
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Cat(slices.zipWithIndex.map { case (s, i) => s.io.l2FlushDone.getOrElse(false.B)}).andR && io_cpu_halt.getOrElse(false.B)
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Cat(slices.zipWithIndex.map { case (s, i) => s.io.l2FlushDone.getOrElse(false.B)}).andR && io_cpu_wfi.getOrElse(false.B)
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}
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/**

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