CHANGELOG

List of major changes and improvements between releases
=======================================================

Yosys 0.63 .. Yosys 0.64-dev
--------------------------

 * Various
    - Removed rarely-used options from ABC/ABC9.
       - Calls to "abc -g AND -fast" to map logic to
         AND-Inverter Graph form should be replaced with
         "aigmap".
       - The above change was made to SBY, so we recommend
         updating it.

Yosys 0.62 .. Yosys 0.63
--------------------------
 * Various
    - Added DSP inference for Gowin GW1N and GW2A.
    - Added support for subtract in preadder for Xilinx arch.
    - Added infrastructure to run a sat solver as a command.

 * New commands and options
    - Added "-ignore-unknown-cells" option to "equiv_induct"
      and "equiv_simple" pass.
    - Added "-force-params" option to "memory_libmap" pass.
    - Added "-select-solver" option to "sat" pass.
    - Added "-default_params" option to "write_verilog" pass.
    - Added "-nodsp" option to "synth_gowin" pass.

Yosys 0.61 .. Yosys 0.62
--------------------------
 * Various
    - verific: Added "-sv2017" flag option to support System
      Verilog 2017.
    - verific: Added VHDL related flags to "-f" and "-F" and
      support reading VHDL file from file lists.
    - Updated cell libs with proper module declaration where
      non standard (...) style was used.

 * New commands and options
    - Added "-word" option to "lut2mux" pass to enable emitting
      word level cells.
    - Added experimental "opt_balance_tree" pass to convert
      cascaded cells into tree of cells to improve timing.
    - Added "-gatesi" option to "write_blif" pass to init gates
      under gates_mode in BLIF format.
    - Added "-on" and "-off" options to "debug" pass for 
      persistent debug logging.
    - Added "linux_perf" pass to control performance recording.

Yosys 0.60 .. Yosys 0.61
--------------------------
 * Various
    - Removed "cover" pass for coverage tracking.
    - Avoid merging formal properties with "opt_merge" pass.
    - Parallelize "opt_merge" pass.

 * New commands and options
    - Added "design_equal" pass to support fuzz-test comparison.
    - Added "lut2bmux" pass to convert $lut to $bmux.
    - Added "-legalize" option to "read_rtlil" pass to prevent 
      semantic errors.

Yosys 0.59 .. Yosys 0.60
--------------------------
 * Various
    - read_verilog: suport unsized parameters.
    - Added static library compile option.

 * New commands and options
    - Added "sdc" pass for reading SDC files.
    - Added experimental "sdc_expand" and "opensta" for OpenSTA integration.
    - Added "icell_liberty" pass for used internal cells.

Yosys 0.58 .. Yosys 0.59
--------------------------
 * Various
    - Pyosys is rewritten using pybind11.
    - alumacc: merge independent of sign.
    - write_btor: Include $assert and $assume cells in -ywmap output.
    - RTLIL parser rewritten for efficiency.
    - Wildcards enabled for Liberty file consuming.
    - timeest: Add top ports launching/sampling.

 * New commands and options
    - Added "-apply_derived_type" option to "box_derive" pass.
    - Added "-publish_icells" option to "chtype" pass.
    - Added "-width" option to "sim" pass.
    - Added "sort" pass for sorting the design objects.
    - Merged "synth_ecp5" and "synth_nexus" into "synth_lattice" pass.
    - Added "-strict-gw5a-dffs" and "-setundef" options to "synth_gowin" pass.

Yosys 0.57 .. Yosys 0.58
--------------------------
 * Various
    - Run ABC passes in parallel.
    - Extending support for buffer normalization.
    - Overhaul of logging APIs.
    - read_blif: Represent sequential elements with gate cells.
    - Support multiple lib files in abc9_exe.

 * New commands and options
    - Added "-wireshape" option to "show" command to allow
      control the shape of wire nodes.
    - Added "-relativeshare" option to "read_verilog", "synth"
      and "techmap" pass for synthesis reproducibility testing.
    - "write_rtlil" pass no longer sorts design, added "-sort"
      option to match old behavior
    - Added "-sva-continue-on-err" to "verific" pass to allow
      processing designs that includes unsupported SVA.

Yosys 0.56 .. Yosys 0.57
--------------------------
 * New commands and options
    - Added "-initstates" option to "abstract" pass.
    - Added "-set-assumes" option to "equiv_induct"
      and "equiv_simple" passes.
    - Added "-always" option to "raise_error" pass.
    - Added "-hierarchy" option to "stat" pass.
    - Added "-noflatten" option to "synth_quicklogic" pass.

 * Various
    - smtbmc: Support skipping steps in cover mode.
    - write_btor: support $buf.
    - read_verilog: support package import.

Yosys 0.55 .. Yosys 0.56
--------------------------
 * New commands and options
    - Added "-unescape" option to "rename" pass.
    - Added "-assert2cover" option to "chformal" pass.
    - Added "linecoverage" pass to generate lcov report from selection.
    - Added "opt_hier" pass to enable hierarchical optimization.
    - Added "-hieropt" option to "synth" pass.
    - Added "-expect-return", "-err-grep" and "-suffix" options
      to "bugpoint" pass.
    - Added "raise_error" dev pass.

 * Various
    - Added groups to command reference documentation.
    - Added bugpoint guide to documentation.
    - verific: correctly reset Verific flags after import.

Yosys 0.54 .. Yosys 0.55
--------------------------
 * Various
    - read_verilog: Implemented SystemVerilog unique/priority if.
    - "attrmap" pass is able to alter memory attributes.
    - verific: Support SVA followed-by operator in cover mode.

Yosys 0.53 .. Yosys 0.54
--------------------------
 * New commands and options
    - Added "-genlib" option to "abc_new" and "abc9_exe" passes.
    - Added "-verbose" and "-quiet" options to "libcache" pass.
    - Added "-no-sort" option to "write_aiger" pass.

 * Various
    - Added "muldiv_c" peepopt.
    - Accept (and ignore) SystemVerilog unique/priority if.
    - "read_verilog" copy inout ports in and out of functions/tasks.
    - Enable single-bit vector wires in RTLIL.

 * Xilinx support
    - Single-port URAM mapping to support memories 2048 x 144b 

Yosys 0.52 .. Yosys 0.53
--------------------------
 * New commands and options
    - Added "constmap" pass for technology mapping of coarse constant value.
    - Added "timeest" pass to estimate the critical path in clock domain.
    - Added "-blackbox" option to "cutpoint" pass to cut all instances of
      blackboxes.
    - Added "-noscopeinfo" option to "cutpoint" pass.
    - Added "-nocleanup" option to "flatten" pass to prevent removal of
      unused submodules.
    - Added "-declockgate" option to "formalff" pass that turns clock
      gating into clock enables.

 * Various
    - Added "$scopeinfo" cells to preserve information during "cutpoint" pass.
    - Added dataflow tracking documentation.
    - share: Restrict activation patterns to potentially relevant signal.
    - liberty: More robust parsing.
    - verific: bit blast RAM if using mem2reg attribute.

Yosys 0.51 .. Yosys 0.52
--------------------------
 * New commands and options
    - Added "-pattern-limit" option to "share" pass to limit analysis effort.
    - Added "libcache" pass to control caching of technology library 
      data parsed from liberty files.
    - Added "read_verilog_file_list" to parse verilog file list.

 * Various
    - Added $macc_v2 cell.
    - Improve lexer performance and zlib support for "read_liberty".
    - opt_expr: optimize pow of 2 cells.


Yosys 0.50 .. Yosys 0.51
--------------------------
 * New commands and options
    - Added "abstract" pass to allow reducing and never increasing
      the constraints on a circuit's behavior in a formal verification setting.

 * Various
    - "splitcells" pass now splits "aldff" cells.
    - FunctionalIR documentation

 * QuickLogic support
    - Added IOFF inference for qlf_k6n10f

 * Intel support
    - Fixed RAM and DSP support.
    - Overall performance improvement for "synth_intel".

Yosys 0.49 .. Yosys 0.50
--------------------------
 * Various
    - "write_verilog" emits "$check" cell names as labels.

Yosys 0.48 .. Yosys 0.49
--------------------------
 * Various
    - "$scopeinfo" cells are now part of JSON export by default.
    - Added option to specify hierarchical separator for "flatten".
    - Improved "wreduce" to handle more cases of operator size reduction.
    - Updated hashing interface, see docs/source/yosys_internals/hashing.rst
      for breaking API changes.

 * New commands and options
    - Added "-noscopeinfo" option to "json" and "write_json" pass.

Yosys 0.47 .. Yosys 0.48
--------------------------
 * Various
    - Removed "read_ilang" deprecated pass.
    - Enhanced boxing features in the experimental "abc_new" command.
    - Added new Tcl methods for design inspection.
    - Added clock enable inference to "dfflibmap".
    - Added a Han-Carlson and Sklansky option for $lcu mapping.

 * New commands and options
    - Added "-nopeepopt" option to "clk2fflogic" pass.
    - Added "-liberty" and "-dont_use" options to "clockgate" pass.
    - Added "-ignore_buses" option to "read_liberty" pass.
    - Added "-dont_map" option to "techmap" pass.
    - Added "-selected" option to "write_json" pass.
    - Added "wrapcell" command for creating wrapper modules
      around selected cells.
    - Added "portarcs" command for deriving propagation timing arcs.
    - Added "setenv" command for setting environment variables.

 * Gowin support
    - Added "-family" option to "synth_gowin" pass.
    - Cell definitions split by family. 

 * Verific support
    - Improved blackbox support.

Yosys 0.46 .. Yosys 0.47
--------------------------
 * Various
    - Added cxxopts library for handling command line arguments.
    - Added docs generation from cells help output.

 * New commands and options
    - Added "-json" option to "synth_xilinx" pass.
    - Added "-derive_luts" option to "cellmatch" pass.
    - Added "t:@<name>" syntax to "select" pass.
    - Added "-list-mod" option to "select" pass.
    - Removed deprecated "qwp" pass.

 * Verific support
    - Initial state handling for VHDL assertions.

Yosys 0.45 .. Yosys 0.46
--------------------------
 * Various
    - Added new "functional backend" infrastructure with three example
      backends (C++, SMTLIB and Rosette).
    - Added new coarse-grain buffer cell type "$buf" to RTLIL.
    - Added "-y" command line option to execute a Python script with 
      libyosys available as a built-in module.
    - Added support for casting to type in Verilog frontend.

 * New commands and options
    - Added "clockgate" pass for automatic clock gating cell insertion.
    - Added "bufnorm" experimental pass to convert design into
      buffered-normalized form.
    - Added experimental "aiger2" and "xaiger2" backends, and an 
      experimental "abc_new" command
    - Added "-force-detailed-loop-check" option to "check" pass.
    - Added "-unit_delay" option to "read_liberty" pass.

 * Verific support
    - Added left and right bound properties to wires when using
      specific VHDL types.

Yosys 0.44 .. Yosys 0.45
--------------------------
 * Various
    - Added cell types help messages.

 * New back-ends
    - Added initial NG-Ultra support. ( synth_nanoxplore )

Yosys 0.43 .. Yosys 0.44
--------------------------
 * Various
    - Added ENABLE_LTO compile option to enable link time
      optimizations.
    - Build support for Haiku OS.

 * New commands and options
    - Added "keep_hierarchy" pass to add attribute with 
      same name to modules based on cost.
    - Added options "-noopt","-bloat" and "-check_cost" to
      "test_cell" pass. 

 * New back-ends
    - Added initial PolarFire support. ( synth_microchip )

Yosys 0.42 .. Yosys 0.43
--------------------------
 * Various
    - C++ compiler with C++17 support is required.
    - Support for IO liberty files for verification.
    - Limit padding from shiftadd for "peepopt" pass.

 * Verific support
    - Support building Yosys with various Verific library
      configurations. Can be built now without YosysHQ 
      specific patch and extension library.

Yosys 0.41 .. Yosys 0.42
--------------------------
 * New commands and options
    - Added "box_derive" pass to derive box modules.
    - Added option "assert-mod-count" to "select" pass. 
    - Added option "-header","-push" and "-pop" to "log" pass. 
 * Intel support
    - Dropped Quartus support in "synth_intel_alm" pass.

Yosys 0.40 .. Yosys 0.41
--------------------------
 * New commands and options
    - Added "cellmatch" pass for picking out standard cells automatically. 

 * Various
    - Extended the experimental incremental JSON API to allow arbitrary
      smtlib subexpressions.
    - Added support for using ABCs library merging when providing multiple
      liberty files.

 * Verific support
    - Expose library name as module attribute.

Yosys 0.39 .. Yosys 0.40
--------------------------
 * New commands and options
    - Added option "-vhdl2019" to "read" and "verific" pass. 

 * Various
    - Major documentation overhaul.
    - Added port statistics to "stat" command.
    - Added new formatting features to cxxrtl backend.

 * Verific support
    - Added better support for VHDL constants import.
    - Added support for VHDL 2009.

Yosys 0.38 .. Yosys 0.39
--------------------------
 * New commands and options
    - Added option "-extra-map" to "synth" pass. 
    - Added option "-dont_use" to "dfflibmap" pass.
    - Added option "-href" to "show" command.
    - Added option "-noscopeinfo" to "flatten" pass.
    - Added option "-scopename" to "flatten" pass.

 * SystemVerilog
    - Added support for packed multidimensional arrays.

 * Various
    - Added "$scopeinfo" cells to preserve information about
      the hierarchy during flattening.
    - Added sequential area output to "stat -liberty".
    - Added ability to record/replay diagnostics in cxxrtl backend.
 
 * Verific support
    - Added attributes to module instantiation.

Yosys 0.37 .. Yosys 0.38
--------------------------
 * New commands and options
    - Added option "-tech" to "opt_lut" pass.
    - Added option "-nokeep_prints" to "hierarchy" pass.
    - Added option "-nolower" to "async2sync" and "clk2fflogic" pass.
    - Added option "-lower" to "chformal" pass.

 * Various
    - Added $check cell to represent assertions with messages.
    - Allow capturing $print cell output in CXXRTL.
    - Added API to overwrite existing pass from plugin.
    - Follow the XDG Base Directory Specification for storing history files.
    - Without a known top module, derive all deferred modules (hierarchy pass).
    - Detect and error out on combinational loops in write_aiger.

 * Verific support
    - Added option "-no-split-complex-ports" to "verific -import".

Yosys 0.36 .. Yosys 0.37
--------------------------
 * New commands and options
    - Added option "-nodisplay" to read_verilog.

 * SystemVerilog
    - Correct hierarchical path names for structs and unions.

 * Various
    - Print hierarchy for failed assertions in "sim" pass.
    - Add "--present-only" option to "yosys-witness" to omit unused signals.
    - Implement a generic record/replay interface for CXXRTL.
    - Improved readability of emitted code with "write_verilog".

Yosys 0.35 .. Yosys 0.36
--------------------------
 * New commands and options
    - Added option "--" to pass arguments down to tcl when using -c option.
    - Added ability on MacOS and Windows to pass options after arguments on cli.
    - Added option "-cmp2softlogic" to synth_lattice.
    - Added option "-lowpower" to "booth" pass.

 * QuickLogic support
    - Added "K6N10f" support.
    - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to 
      "synth_quicklogic" pass.
    - Added "ql_bram_merge" pass to merge 18K BRAM cells into TDP36K.
    - Added "ql_bram_types" pass to change TDP36K depending on configuration.
    - Added "ql_dsp_io_regs" pass to update QL_DSP2 depending on configuration.
    - Added "ql_dsp_macc" pass to infer multiplier-accumulator DSP cells.
    - Added "ql_dsp_simd" pass to merge DSP pairs to operate in SIMD mode.

 * ECP5,iCE40 and Gowin support
    - Enabled abc9 by default, added "-noabc9" option to disable.

 * MachXO3 support
    - Quality of results improvements.
    - Enabled "booth" pass by default for it in "synth_lattice".

 * Various
    - Improved "peepopt" by adding shiftadd pattern support.
    - Added "--incremental" mode to smtbmc.

Yosys 0.34 .. Yosys 0.35
--------------------------
 * Various
    - Improvements on "peepopt" shiftmul matcher.
    - Improvements on "ram_style" attributes handling.

 * Verific support
    - Improved static elaboration for VHDL and mixed HDL designs.
    - Expose "hdlname" attribute with original module name.
    - Expose "architecture" attribute with VHDL architecture name.

Yosys 0.33 .. Yosys 0.34
--------------------------
 * New commands and options
    - Added option "-assert" to "sim" pass.
    - Added option "-noinitstate" to "sim" pass.
    - Added option "-dont_use" to "abc" pass.
    - Added "dft_tag" pass to create tagging logic for data flow tracking.
    - Added "future" pass to resolve future sampled value functions.
    - Added "booth" pass to map $mul cells to Booth multipliers.
    - Added option "-booth" to "synth" pass.

 * SystemVerilog
    - Added support for assignments within expressions, e.g., `x[y++] = z;` or
      `x = (y *= 2) - 1;`.

 * Verific support
    - "src" attribute contain full location info.
    - module parameters are kept after import.
    - accurate access order semantics in memory inference.
    - better "bind" support for mixed language projects.

 * Various
    - "show" command displays dot instead of box for wire aliases.

Yosys 0.32 .. Yosys 0.33
--------------------------
 * Various
    - Added "$print" cell, produced by "$display" and "$write"
      Verilog tasks.
    - Added "$print" cell handling in CXXRTL.

 * Lattice FPGA support
    - Added generic "synth_lattice" pass (for now MachXO2/XO3/XO3D)
    - Removed "synth_machxo2" pass
    - Pass "ecp5_gsr" renamed to "lattice_gsr"
    - "synth_machxo2" equivalent is "synth_lattice -family xo2"

Yosys 0.31 .. Yosys 0.32
--------------------------
 * Verific support
    - Added sub option "-lib" to reading commands for VHDL and
      SystemVerilog, that will later import all units/modules from
      marked files as blackboxes.

 * Various
    - Added support for $lt, $le, $gt, $ge to the code generating AIGs.

Yosys 0.30 .. Yosys 0.31
--------------------------
 * New commands and options
    - Added option "-lsbidx" to "write_edif" pass.

 * Various
    - Added support for $divfloor operator to cxxrtl backend.
    - dfflegalize: allow setting mince and minsrst args from scratchpad.

Yosys 0.29 .. Yosys 0.30
--------------------------
 * New commands and options
    - Added "recover_names" pass to recover names post-mapping.

 * Gowin support
    - Added remaining primitives blackboxes.

 * Various
    - "show -colorattr" will now color the cells, wires, and 
      connection arrows.
    - "show -viewer none" will not execute viewer.

Yosys 0.28 .. Yosys 0.29
--------------------------
 * New commands and options
    - Added "synthprop" pass for synthesizable properties.

 * Verific support
    - Handle conditions on clocked concurrent assertions in unclocked
      procedural contexts.

 * Verilog
    - Fix const eval of unbased unsized constants.
    - Handling of attributes for struct / union variables.

Yosys 0.27 .. Yosys 0.28
--------------------------
 * Verilog
    - Out of bounds checking for struct/union members.

 * Verific support
    - Fix enum_values support and signed attribute values.

 * ECP5 support
    - Added "synth_ecp5 -iopad"

 * MachXO2 support
    - Added "synth_machxo2 -ccu2"

Yosys 0.26 .. Yosys 0.27
--------------------------
 * New commands and options
    - Added option "-make_assert" to "equiv_make" pass.
    - Added option "-coverenable" to "chformal" pass.

 * Verilog
    - Resolve package types in interfaces.
    - Handle range offsets in packed arrays within packed structs.
    - Support for data and array queries on struct/union item expressions.

 * GateMate support
    - Enable register initialization.

Yosys 0.25 .. Yosys 0.26
--------------------------
 * New commands and options
    - Added "bwmuxmap" pass to replace $bwmux cells with equivalent logic.
    - Added "xprop" experimental pass for formal x propagation.
    - Added "splitcells" pass to split up multi-bit cells.
    - Added "viz" pass to visualize data flow graph.
    - Added option "-make_cover" to "miter" pass.
    - Added option "-noparallelcase" to "write_verilog" pass.
    - Added option "-chain" to "insbuf" pass.
    - Added options "-hierarchy" and "-assume" to "formalff" pass.
    - Added options "-append" and "-summary" to "sim" pass.
    - Added option "-ywmap" to "write_btor" pass.
    - Added option "-ignore-self-reset" to "fsm_detect" pass.

 * Verilog
    - Support for struct members of union type.
    - Support for struct member package types.

 * Various
    - Added Yosys witness (.yw) cosimulation.
    - GCC 4.8 is deprecated, compiler with full C++11 support is required.

Yosys 0.24 .. Yosys 0.25
--------------------------
 * Verific support
    - Respect "noblackbox" attribute for modules.

 * Various
    - Documentation is hosted at https://yosyshq.readthedocs.io/projects/yosys/en/latest/

Yosys 0.23 .. Yosys 0.24
--------------------------
 * New commands and options
    - Added option "-set-def-formal" to "sat" pass.
    - Added option "-s" to "tee" command.

 * Verilog
    - Support for module-scoped identifiers referring to tasks and functions.
    - Support for arrays with swapped ranges within structs.

 * Verific support
    - Support for importing verilog configurations per name.
    - "verific -set-XXXXX" commands are now able to set severity to all messages
      of certain type (errors, warnings, infos and comments)

 * Various
    - TCL shell support (use "yosys -C")
    - Added FABulous eFPGA frontend

Yosys 0.22 .. Yosys 0.23
--------------------------
 * New commands and options
    - Added option "-cross" to "miter" pass.
    - Added option "-nocheck" to "equiv_opt" pass.

 * Formal Verification
    - yosys-smtbmc: Added "--detect-loops" option for checking if states are
      unique in temporal induction counter examples.

 * Verific support
    - Added support for reading Liberty files using Verific library.
      (Optinally enabled with ENABLE_VERIFIC_LIBERTY)
    - Added option "-cells" to "verific -import" enabling import of
      all cells from verific design.

 * Various
    - MinGW build (Windows) plugin support.
    - Added YOSYS_ABORT_ON_LOG_ERROR environment variable for debugging.
      Setting it to 1 causes abort() to be called when Yosys terminates with an
      error message.

Yosys 0.21 .. Yosys 0.22
--------------------------
 * Verific support
    - Added support for here-document for "verific" command (for reading
      source files).
    - Added support for reading EDIF files using Verific library.
      (Optinally enabled with ENABLE_VERIFIC_EDIF)

 * Various
    - Added tech specific utilization to "stat" json.

Yosys 0.20 .. Yosys 0.21
--------------------------
 * New commands and options
    - Added "formalff" pass - transforms FFs for formal verification
    - Added option "-formal" to "memory_map" pass
    - Added option "-witness" to "rename" - give public names to all signals
      present in yosys witness traces
    - Added option "-hdlname" to "sim" pass - preserves hiearachy when writing
      simulation output for a flattened design
    - Addded option "-scramble-name" to "rename" pass

 * Formal Verification
    - Added $anyinit cell to directly represent FFs with an unconstrained
      initialization value. These can be generated by the new formalff pass.
    - New JSON based yosys witness format for formal verification traces.
    - yosys-smtbmc: Reading and writing of yosys witness traces.
    - write_smt2: Emit inline metadata to support yosys witness trace.
    - yosys-witness is a new tool to inspect and convert yosys witness traces.
    - write_aiger: Option to write a map file for yosys witness trace
      conversion.
    - yosys-witness: Conversion from and to AIGER witness traces.

 * Verific support
    - Filename re-writing support for "verific" pass.

 * Various
    - ABC performance improvements
    - Filename re-writing added for "show -lib".

 * SmartFusion2 support
    - Added $alu support
    - Added SYSRESET and XTLOSC cells
    - Compatible now with LiberoSoc flow

Yosys 0.19 .. Yosys 0.20
--------------------------
 * New commands and options
    - Added option "-wb" to "read_liberty" pass

 * Various
    - Added support for $modfloor operator to cxxrtl backend
    - Support build on OpenBSD
    - Fixed smt2 backend use of $shift/$shiftx with negative shift amounts,
      which affects bit/part-select assignments with a dynamic index. Shift
      operators were not affected.

 * Verific support
    - Proper import of port ranges into Yosys, may result in reversed 
      bit-order of top-level ports for some synthesis flows.

Yosys 0.18 .. Yosys 0.19
--------------------------
 * New commands and options
    - Added option "-rom-only" to "memory_libmap" pass
    - Added option "-smtcheck" to "hierarchy" pass
    - Added option "-keepdc" to "memory_libmap" pass
    - Added option "-suffix" to "rename" pass
    - Added "gatemate_foldinv" pass

 * Formal Verification
    - Added support for $pos cell in btor backend
    - Added the "smtlib2_module" and "smtlib2_comb_expr" attributes

 * GateMate support
    - Added LUT tree mapping

 * Verific support
    - Added option "-pp" to "verific -import"

Yosys 0.17 .. Yosys 0.18
--------------------------
 * Various
    - Migrated most flows to use memory_libmap based memory inference

 * New commands and options
    - Added "memory_libmap" pass
    - Added "memory_bmux2rom" pass - converts muxes to ROMs
    - Added "memory_dff -no-rw-check"
    - Added "opt_ffinv" pass - push inverters through FFs
    - Added "proc_rom" pass - convert switches to ROMs
    - Added "proc -norom" option - will omit the proc_rom pass
    - Added option "-no-rw-check" to synth passes
    - Added "synth_ice40 -spram" option for automatic inference of SB_SPRAM256KA
    - Added options "-nobram" and "-nolutram" to synth_machxo2 pass

 * Formal Verification
    - Fixed the signedness of $past's return value to be the same as the
      argument's instead of always unsigned.

 * Verilog
    - Fixed an issue where simplifying case statements by removing unreachable
      cases could result in the wrong signedness being used for comparison with
      the remaining cases
    - Fixed size and signedness computation for expressions containing array
      querying functions
    - Fixed size and signedness computation of functions used in ternary
      expressions or case item expressions

 * Verific support
    - Proper file location for readmem commands
    - Added "-vlog-libext" option to specify search extension for libraries

Yosys 0.16 .. Yosys 0.17
--------------------------
 * New commands and options
    - Added "write_jny" ( JSON netlist metadata format )
    - Added "tribuf -formal"

 * SystemVerilog
    - Fixed automatic `nosync` inference for local variables in `always_comb`
      procedures not applying to nested blocks and blocks in functions

Yosys 0.15 .. Yosys 0.16
--------------------------
 * Various
    - Added BTOR2 witness file co-simulation.
    - Simulation calls external vcd2fst for VCD conversion.
    - Added fst2tb pass - generates testbench for the circuit using
      the given top-level module and simulus signal from FST file.
    - yosys-smtbmc: Option to keep going after failed assertions in BMC mode

 * Verific support
    - Import modules in alphabetic (reproducable) order.

Yosys 0.14 .. Yosys 0.15
--------------------------

 * Various
    - clk2fflogic: nice names for autogenerated signals
    - simulation include support for all flip-flop types.
    - Added AIGER witness file co-simulation.

 * Verilog
    - Fixed evaluation of constant functions with variables or arguments with
      reversed dimensions
    - Fixed elaboration of dynamic range assignments where the vector is
      reversed or is not zero-indexed
    - Added frontend support for time scale delay values (e.g., `#1ns`)

 * SystemVerilog
    - Added support for accessing whole sub-structures in expressions
 
 * New commands and options
    - Added glift command, used to create gate-level information flow tracking
      (GLIFT) models by the "constructive mapping" approach

 * Verific support
    - Ability to override default parser mode for verific -f command.

Yosys 0.13 .. Yosys 0.14
--------------------------

 * Various
    - Added $bmux and $demux cells and related optimization patterns.

 * New commands and options
    - Added "bmuxmap" and "dmuxmap" passes 
    - Added "-fst" option to "sim" pass for writing FST files
    - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
      "-sim-gold" options to "sim" pass for co-simulation

 * Anlogic support
    - Added support for BRAMs

Yosys 0.12 .. Yosys 0.13
--------------------------

 * Various
    - Use "read" command to parse HDL files from Yosys command-line
    - Added "yosys -r <topmodule>" command line option
    - write_verilog: dump zero width sigspecs correctly

 * SystemVerilog
    - Fixed regression preventing the use array querying functions in case
      expressions and case item expressions
    - Fixed static size casts inadvertently limiting the result width of binary
      operations
    - Fixed static size casts ignoring expression signedness
    - Fixed static size casts not extending unbased unsized literals
    - Added automatic `nosync` inference for local variables in `always_comb`
      procedures which are always assigned before they are used to avoid errant
      latch inference

 * New commands and options
    - Added "clean_zerowidth" pass

 * Verific support
    - Add YOSYS to the implicitly defined verilog macros in verific

Yosys 0.11 .. Yosys 0.12
--------------------------

 * Various
    - Added iopadmap native support for negative-polarity output enable
    - ABC update

 * SystemVerilog
    - Support parameters using struct as a wiretype

 * New commands and options
    - Added "-genlib" option to "abc" pass
    - Added "sta" very crude static timing analysis pass

 * Verific support
    - Fixed memory block size in import

 * New back-ends
    - Added support for GateMate FPGA from Cologne Chip AG

 * Intel ALM support
    - Added preliminary Arria V support


Yosys 0.10 .. Yosys 0.11
--------------------------

 * Various
    - Added $aldff and $aldffe (flip-flops with async load) cells

 * SystemVerilog
    - Fixed an issue which prevented writing directly to a memory word via a
      connection to an output port
    - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
      filling the width of a cell input
    - Fixed an issue where connecting a slice covering the entirety of a signed
      signal to a cell input would cause a failed assertion

 * Verific support
    - Importer support for {PRIM,WIDE_OPER}_DFF
    - Importer support for PRIM_BUFIF1
    - Option to use Verific without VHDL support
    - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
    - Added -cfg option for getting/setting Verific runtime flags

Yosys 0.9 .. Yosys 0.10
--------------------------

 * Various
    - Added automatic gzip decompression for frontends
    - Added $_NMUX_ cell type
    - Added automatic gzip compression (based on filename extension) for backends
    - Improve attribute and parameter encoding in JSON to avoid ambiguities between
      bit vectors and strings containing [01xz]*
    - Improvements in pmgen: subpattern and recursive matches
    - Support explicit FIRRTL properties
    - Improvements in pmgen: slices, choices, define, generate
    - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
    - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
    - Added new frontend: rpc
    - Added --version and -version as aliases for -V
    - Improve yosys-smtbmc "solver not found" handling
    - Improved support of $readmem[hb] Memory Content File inclusion
    - Added CXXRTL backend
    - Use YosysHQ/abc instead of upstream berkeley-abc/abc
    - Added WASI platform support.
    - Added extmodule support to firrtl backend
    - Added $divfloor and $modfloor cells
    - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
    - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
    - Added firrtl backend support for generic parameters in blackbox components
    - Added $meminit_v2 cells (with support for write mask)
    - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
      - write priority masks, per write/write port pair
      - transparency and undefined collision behavior masks, per read/write port pair
      - read port reset and initialization
      - wide ports (accessing a naturally aligned power-of-two number of memory cells)

 * New commands and options
    - Added "write_xaiger" backend
    - Added "read_xaiger"
    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
    - Added "synth -abc9" (experimental)
    - Added "script -scriptwire"
    - Added "clkbufmap" pass
    - Added "extractinv" pass and "invertible_pin" attribute
    - Added "proc_clean -quiet"
    - Added "proc_prune" pass
    - Added "stat -tech cmos"
    - Added "opt_share" pass, run as part of "opt -full"
    - Added "-match-init" option to "dff2dffs" pass
    - Added "equiv_opt -multiclock"
    - Added "techmap_autopurge" support to techmap
    - Added "add -mod <modname[s]>"
    - Added "paramap" pass
    - Added "portlist" command
    - Added "check -mapped"
    - Added "check -allow-tbuf"
    - Added "autoname" pass
    - Added "write_verilog -extmem"
    - Added "opt_mem" pass
    - Added "scratchpad" pass
    - Added "fminit" pass
    - Added "opt_lut_ins" pass
    - Added "logger" pass
    - Added "show -nobg"
    - Added "exec" command
    - Added "design -delete"
    - Added "design -push-copy"
    - Added "qbfsat" command
    - Added "select -unset"
    - Added "dfflegalize" pass
    - Removed "opt_expr -clkinv" option, made it the default
    - Added "proc -nomux
    - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass

 * SystemVerilog
    - Added checking of always block types (always_comb, always_latch and always_ff)
    - Added support for wildcard port connections (.*)
    - Added support for enum typedefs
    - Added support for structs and packed unions.
    - Allow constant function calls in for loops and generate if and case
    - Added support for static cast
    - Added support for logic typed parameters
    - Fixed generate scoping issues
    - Added support for real-valued parameters
    - Allow localparams in constant functions
    - Module name scope support
    - Support recursive functions using ternary expressions
    - Extended support for integer types
    - Support for parameters without default values
    - Allow globals in one file to depend on globals in another
    - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
    - Added support for parsing the 'bind' construct
    - support declaration in procedural for initialization
    - support declaration in generate for initialization
    - Support wand and wor of data types

 * Verific support
    - Added "verific -L"
    - Add Verific SVA support for "always" properties
    - Add Verific support for SVA nexttime properties
    - Improve handling of verific primitives in "verific -import -V" mode
    - Import attributes for wires
    - Support VHDL enums
    - Added support for command files

 * New back-ends
    - Added initial EFINIX support
    - Added Intel ALM: alternative synthesis for Intel FPGAs
    - Added initial Nexus support
    - Added initial MachXO2 support
    - Added initial QuickLogic PolarPro 3 support

 * ECP5 support
    - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
    - Added "synth_ecp5 -abc9" (experimental)
    - Added "synth_ecp5 -nowidelut"
    - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)

 * iCE40 support
    - Added "synth_ice40 -abc9" (experimental)
    - Added "synth_ice40 -device"
    - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
    - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
    - Removed "ice40_unlut"
    - Added "ice40_dsp" for Lattice iCE40 DSP packing
    - "synth_ice40 -dsp" to infer DSP blocks

 * Xilinx support
    - Added "synth_xilinx -abc9" (experimental)
    - Added "synth_xilinx -nocarry"
    - Added "synth_xilinx -nowidelut"
    - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
    - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
    - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
    - Added "synth_xilinx -ise" (experimental)
    - Added "synth_xilinx -iopad"
    - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
    - Added "xilinx_srl" for Xilinx shift register extraction
    - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
    - Added "xilinx_dsp" for Xilinx DSP packing
    - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
    - Added latch support to synth_xilinx
    - Added support for flip-flops with synchronous reset to synth_xilinx
    - Added support for flip-flops with reset and enable to synth_xilinx
    - Added "xilinx_dffopt" pass
    - Added "synth_xilinx -dff"

 * Intel support
    - Renamed labels in synth_intel (e.g. bram -> map_bram)
    - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
    - Added "intel_alm -abc9" (experimental)

 * CoolRunner2 support
    - Separate and improve buffer cell insertion pass
    - Use extract_counter to optimize counters

Yosys 0.8 .. Yosys 0.9
----------------------

 * Various
    - Many bugfixes and small improvements
    - Added support for SystemVerilog interfaces and modports
    - Added "write_edif -attrprop"
    - Added "opt_lut" pass
    - Added "gate2lut.v" techmap rule
    - Added "rename -src"
    - Added "equiv_opt" pass
    - Added "flowmap" LUT mapping pass
    - Added "rename -wire" to rename cells based on the wires they drive
    - Added "bugpoint" for creating minimised testcases
    - Added "write_edif -gndvccy"
    - "write_verilog" to escape Verilog keywords
    - Fixed sign handling of real constants
    - "write_verilog" to write initial statement for initial flop state
    - Added pmgen pattern matcher generator
    - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
    - Added "setundef -params" to replace undefined cell parameters
    - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
    - Fixed handling of defparam when default_nettype is none
    - Fixed "wreduce" flipflop handling
    - Fixed FIRRTL to Verilog process instance subfield assignment
    - Added "write_verilog -siminit"
    - Several fixes and improvements for mem2reg memories
    - Fixed handling of task output ports in clocked always blocks
    - Improved handling of and-with-1 and or-with-0 in "opt_expr"
    - Added "read_aiger" frontend
    - Added "mutate" pass
    - Added "hdlname" attribute
    - Added "rename -output"
    - Added "read_ilang -lib"
    - Improved "proc" full_case detection and handling
    - Added "whitebox" and "lib_whitebox" attributes
    - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
    - Added Python bindings and support for Python plug-ins
    - Added "pmux2shiftx"
    - Added log_debug framework for reduced default verbosity
    - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
    - Added "peepopt" peephole optimisation pass using pmgen
    - Added approximate support for SystemVerilog "var" keyword
    - Added parsing of "specify" blocks into $specrule and $specify[23]
    - Added support for attributes on parameters and localparams
    - Added support for parsing attributes on port connections
    - Added "wreduce -keepdc"
    - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
    - Added Verilog wand/wor wire type support
    - Added support for elaboration system tasks
    - Added "muxcover -mux{4,8,16}=<cost>"
    - Added "muxcover -dmux=<cost>"
    - Added "muxcover -nopartial"
    - Added "muxpack" pass
    - Added "pmux2shiftx -norange"
    - Added support for "~" in filename parsing
    - Added "read_verilog -pwires" feature to turn parameters into wires
    - Fixed sign extension of unsized constants with 'bx and 'bz MSB
    - Fixed genvar to be a signed type
    - Added support for attributes on case rules
    - Added "upto" and "offset" to JSON frontend and backend
    - Several liberty file parser improvements
    - Fixed handling of more complex BRAM patterns
    - Add "write_aiger -I -O -B"

 * Formal Verification
    - Added $changed support to read_verilog
    - Added "read_verilog -noassert -noassume -assert-assumes"
    - Added btor ops for $mul, $div, $mod and $concat
    - Added yosys-smtbmc support for btor witnesses
    - Added "supercover" pass
    - Fixed $global_clock handling vs autowire
    - Added $dffsr support to "async2sync"
    - Added "fmcombine" pass
    - Added memory init support in "write_btor"
    - Added "cutpoint" pass
    - Changed "ne" to "neq" in btor2 output
    - Added support for SVA "final" keyword
    - Added "fmcombine -initeq -anyeq"
    - Added timescale and generated-by header to yosys-smtbmc vcd output
    - Improved BTOR2 handling of undriven wires

 * Verific support
    - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
    - Improved support for asymmetric memories
    - Added "verific -chparam"
    - Fixed "verific -extnets" for more complex situations
    - Added "read -verific" and "read -noverific"
    - Added "hierarchy -chparam"

 * New back-ends
    - Added initial Anlogic support
    - Added initial SmartFusion2 and IGLOO2 support

 * ECP5 support
    - Added "synth_ecp5 -nowidelut"
    - Added BRAM inference support to "synth_ecp5"
    - Added support for transforming Diamond IO and flipflop primitives

 * iCE40 support
    - Added "ice40_unlut" pass
    - Added "synth_ice40 -relut"
    - Added "synth_ice40 -noabc"
    - Added "synth_ice40 -dffe_min_ce_use"
    - Added DSP inference support using pmgen
    - Added support for initialising BRAM primitives from a file
    - Added iCE40 Ultra RGB LED driver cells

 * Xilinx support
    - Use "write_edif -pvector bra" for Xilinx EDIF files
    - Fixes for VPR place and route support with "synth_xilinx"
    - Added more cell simulation models
    - Added "synth_xilinx -family"
    - Added "stat -tech xilinx" to estimate logic cell usage
    - Added "synth_xilinx -nocarry"
    - Added "synth_xilinx -nowidelut"
    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
    - Added support for mapping RAM32X1D

Yosys 0.7 .. Yosys 0.8
----------------------

 * Various
    - Many bugfixes and small improvements
    - Strip debug symbols from installed binary
    - Replace -ignore_redef with -[no]overwrite in front-ends
    - Added write_verilog hex dump support, add -nohex option
    - Added "write_verilog -decimal"
    - Added "scc -set_attr"
    - Added "verilog_defines" command
    - Remember defines from one read_verilog to next
    - Added support for hierarchical defparam
    - Added FIRRTL back-end
    - Improved ABC default scripts
    - Added "design -reset-vlog"
    - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
    - Added Verilog $rtoi and $itor support
    - Added "check -initdrv"
    - Added "read_blif -wideports"
    - Added support for SystemVerilog "++" and "--" operators
    - Added support for SystemVerilog unique, unique0, and priority case
    - Added "write_edif" options for edif "flavors"
    - Added support for resetall compiler directive
    - Added simple C beck-end (bitwise combinatorical only atm)
    - Added $_ANDNOT_ and $_ORNOT_ cell types
    - Added cell library aliases to "abc -g"
    - Added "setundef -anyseq"
    - Added "chtype" command
    - Added "design -import"
    - Added "write_table" command
    - Added "read_json" command
    - Added "sim" command
    - Added "extract_fa" and "extract_reduce" commands
    - Added "extract_counter" command
    - Added "opt_demorgan" command
    - Added support for $size and $bits SystemVerilog functions
    - Added "blackbox" command
    - Added "ltp" command
    - Added support for editline as replacement for readline
    - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
    - Added "yosys -E" for creating Makefile dependencies files
    - Added "synth -noshare"
    - Added "memory_nordff"
    - Added "setundef -undef -expose -anyconst"
    - Added "expose -input"
    - Added specify/specparam parser support (simply ignore them)
    - Added "write_blif -inames -iattr"
    - Added "hierarchy -simcheck"
    - Added an option to statically link abc into yosys
    - Added protobuf back-end
    - Added BLIF parsing support for .conn and .cname
    - Added read_verilog error checking for reg/wire/logic misuse
    - Added "make coverage" and ENABLE_GCOV build option

 * Changes in Yosys APIs
    - Added ConstEval defaultval feature
    - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
    - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
    - Added log_file_warning() and log_file_error() functions

 * Formal Verification
    - Added "write_aiger"
    - Added "yosys-smtbmc --aig"
    - Added "always <positive_int>" to .smtc format
    - Added $cover cell type and support for cover properties
    - Added $fair/$live cell type and support for liveness properties
    - Added smtbmc support for memory vcd dumping
    - Added "chformal" command
    - Added "write_smt2 -stbv" and "write_smt2 -stdt"
    - Fix equiv_simple, old behavior now available with "equiv_simple -short"
    - Change to Yices2 as default SMT solver (it is GPL now)
    - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
    - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
    - Added a brand new "write_btor" command for BTOR2
    - Added clk2fflogic memory support and other improvements
    - Added "async memory write" support to write_smt2
    - Simulate clock toggling in yosys-smtbmc VCD output
    - Added $allseq/$allconst cells for EA-solving
    - Make -nordff the default in "prep"
    - Added (* gclk *) attribute
    - Added "async2sync" pass for single-clock designs with async resets

 * Verific support
    - Many improvements in Verific front-end
    - Added proper handling of concurent SVA properties
    - Map "const" and "rand const" to $anyseq/$anyconst
    - Added "verific -import -flatten" and "verific -import -extnets"
    - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
    - Remove PSL support (because PSL has been removed in upstream Verific)
    - Improve integration with "hierarchy" command design elaboration
    - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
    - Added simpilied "read" command that automatically uses verific if available
    - Added "verific -set-<severity> <msg_id>.."
    - Added "verific -work <libname>"

 * New back-ends
    - Added initial Coolrunner-II support
    - Added initial eASIC support
    - Added initial ECP5 support

 * GreenPAK Support
    - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.

 * iCE40 Support
    - Add "synth_ice40 -vpr"
    - Add "synth_ice40 -nodffe"
    - Add "synth_ice40 -json"
    - Add Support for UltraPlus cells

 * MAX10 and Cyclone IV Support
    - Added initial version of metacommand "synth_intel".
    - Improved write_verilog command to produce VQM netlist for Quartus Prime.
    - Added support for MAX10 FPGA family synthesis.
    - Added support for Cyclone IV family synthesis.
    - Added example of implementation for DE2i-150 board.
    - Added example of implementation for MAX10 development kit.
    - Added LFSR example from Asic World.
    - Added "dffinit -highlow" for mapping to Intel primitives


Yosys 0.6 .. Yosys 0.7
----------------------

 * Various
    - Added "yosys -D" feature
    - Added support for installed plugins in $(DATDIR)/plugins/
    - Renamed opt_const to opt_expr
    - Renamed opt_share to opt_merge
    - Added "prep -flatten" and "synth -flatten"
    - Added "prep -auto-top" and "synth -auto-top"
    - Using "mfs" and "lutpack" in ABC lut mapping
    - Support for abstract modules in chparam
    - Cleanup abstract modules at end of "hierarchy -top"
    - Added tristate buffer support to iopadmap
    - Added opt_expr support for div/mod by power-of-two
    - Added "select -assert-min <N> -assert-max <N>"
    - Added "attrmvcp" pass
    - Added "attrmap" command
    - Added "tee +INT -INT"
    - Added "zinit" pass
    - Added "setparam -type"
    - Added "shregmap" pass
    - Added "setundef -init"
    - Added "nlutmap -assert"
    - Added $sop cell type and "abc -sop -I <num> -P <num>"
    - Added "dc2" to default ABC scripts
    - Added "deminout"
    - Added "insbuf" command
    - Added "prep -nomem"
    - Added "opt_rmdff -keepdc"
    - Added "prep -nokeepdc"
    - Added initial version of "synth_gowin"
    - Added "fsm_expand -full"
    - Added support for fsm_encoding="user"
    - Many improvements in GreenPAK4 support
    - Added black box modules for all Xilinx 7-series lib cells
    - Added synth_ice40 support for latches via logic loops
    - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"

 * Build System
    - Added ABCEXTERNAL and ABCURL make variables
    - Added BINDIR, LIBDIR, and DATDIR make variables
    - Added PKG_CONFIG make variable
    - Added SEED make variable (for "make test")
    - Added YOSYS_VER_STR make variable
    - Updated min GCC requirement to GCC 4.8
    - Updated required Bison version to Bison 3.x

 * Internal APIs
    - Added ast.h to exported headers
    - Added ScriptPass helper class for script-like passes
    - Added CellEdgesDatabase API

 * Front-ends and Back-ends
    - Added filename glob support to all front-ends
    - Added avail (black-box) module params to ilang format
    - Added $display %m support
    - Added support for $stop Verilog system task
    - Added support for SystemVerilog packages
    - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
    - Added support for "active high" and "active low" latches in read_blif and write_blif
    - Use init value "2" for all uninitialized FFs in BLIF back-end
    - Added "read_blif -sop"
    - Added "write_blif -noalias"
    - Added various write_blif options for VTR support
    - write_json: also write module attributes.
    - Added "write_verilog -nodec -nostr -defparam"
    - Added "read_verilog -norestrict -assume-asserts"
    - Added support for bus interfaces to "read_liberty -lib"
    - Added liberty parser support for types within cell decls
    - Added "write_verilog -renameprefix -v"
    - Added "write_edif -nogndvcc"

 * Formal Verification
    - Support for hierarchical designs in smt2 back-end
    - Yosys-smtbmc: Support for hierarchical VCD dumping
    - Added $initstate cell type and vlog function
    - Added $anyconst and $anyseq cell types and vlog functions
    - Added printing of code loc of failed asserts to yosys-smtbmc
    - Added memory_memx pass, "memory -memx", and "prep -memx"
    - Added "proc_mux -ifx"
    - Added "yosys-smtbmc -g"
    - Deprecated "write_smt2 -regs" (by default on now)
    - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
    - Added support for memories to smtio.py
    - Added "yosys-smtbmc --dump-vlogtb"
    - Added "yosys-smtbmc --smtc --dump-smtc"
    - Added "yosys-smtbmc --dump-all"
    - Added assertpmux command
    - Added "yosys-smtbmc --unroll"
    - Added $past, $stable, $rose, $fell SVA functions
    - Added "yosys-smtbmc --noinfo and --dummy"
    - Added "yosys-smtbmc --noincr"
    - Added "yosys-smtbmc --cex <filename>"
    - Added $ff and $_FF_ cell types
    - Added $global_clock verilog syntax support for creating $ff cells
    - Added clk2fflogic


Yosys 0.5 .. Yosys 0.6
----------------------

 * Various
     - Added Contributor Covenant Code of Conduct
     - Various improvements in dict<> and pool<>
     - Added hashlib::mfp and refactored SigMap
     - Improved support for reals as module parameters
     - Various improvements in SMT2 back-end
     - Added "keep_hierarchy" attribute
     - Verilog front-end: define `BLACKBOX in -lib mode
     - Added API for converting internal cells to AIGs
     - Added ENABLE_LIBYOSYS Makefile option
     - Removed "techmap -share_map" (use "-map +/filename" instead)
     - Switched all Python scripts to Python 3
     - Added support for $display()/$write() and $finish() to Verilog front-end
     - Added "yosys-smtbmc" formal verification flow
     - Added options for clang sanitizers to Makefile

 * New commands and options
     - Added "scc -expect <N> -nofeedback"
     - Added "proc_dlatch"
     - Added "check"
     - Added "select %xe %cie %coe %M %C %R"
     - Added "sat -dump_json" (WaveJSON format)
     - Added "sat -tempinduct-baseonly -tempinduct-inductonly"
     - Added "sat -stepsize" and "sat -tempinduct-step"
     - Added "sat -show-regs -show-public -show-all"
     - Added "write_json" (Native Yosys JSON format)
     - Added "write_blif -attr"
     - Added "dffinit"
     - Added "chparam"
     - Added "muxcover"
     - Added "pmuxtree"
     - Added memory_bram "make_outreg" feature
     - Added "splice -wires"
     - Added "dff2dffe -direct-match"
     - Added simplemap $lut support
     - Added "read_blif"
     - Added "opt_share -share_all"
     - Added "aigmap"
     - Added "write_smt2 -mem -regs -wires"
     - Added "memory -nordff"
     - Added "write_smv"
     - Added "synth -nordff -noalumacc"
     - Added "rename -top new_name"
     - Added "opt_const -clkinv"
     - Added "synth -nofsm"
     - Added "miter -assert"
     - Added "read_verilog -noautowire"
     - Added "read_verilog -nodpi"
     - Added "tribuf"
     - Added "lut2mux"
     - Added "nlutmap"
     - Added "qwp"
     - Added "test_cell -noeval"
     - Added "edgetypes"
     - Added "equiv_struct"
     - Added "equiv_purge"
     - Added "equiv_mark"
     - Added "equiv_add -try -cell"
     - Added "singleton"
     - Added "abc -g -luts"
     - Added "torder"
     - Added "write_blif -cname"
     - Added "submod -copy"
     - Added "dffsr2dff"
     - Added "stat -liberty"

 * Synthesis metacommands
     - Various improvements in synth_xilinx
     - Added synth_ice40 and synth_greenpak4
     - Added "prep" metacommand for "synthesis lite"

 * Cell library changes
     - Added cell types to "help" system
     - Added $meminit cell type
     - Added $assume cell type
     - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
     - Added $tribuf and $_TBUF_ cell types
     - Added read-enable to memory model

 * YosysJS
     - Various improvements in emscripten build
     - Added alternative webworker-based JS API
     - Added a few example applications


Yosys 0.4 .. Yosys 0.5
----------------------

 * API changes
     - Added log_warning()
     - Added eval_select_args() and eval_select_op()
     - Added cell->known(), cell->input(portname), cell->output(portname)
     - Skip blackbox modules in design->selected_modules()
     - Replaced std::map<> and std::set<> with dict<> and pool<>
     - New SigSpec::extend() is what used to be SigSpec::extend_u0()
     - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN

 * Cell library changes
     - Added flip-flops with enable ($dffe etc.)
     - Added $equiv cells for equivalence checking framework

 * Various
     - Updated ABC to hg rev 61ad5f908c03
     - Added clock domain partitioning to ABC pass
     - Improved plugin building (see "yosys-config --build")
     - Added ENABLE_NDEBUG Makefile flag for high-performance builds
     - Added "yosys -d", "yosys -L" and other driver improvements
     - Added support for multi-bit (array) cell ports to "write_edif"
     - Now printing most output to stdout, not stderr
     - Added "onehot" attribute (set by "fsm_map")
     - Various performance improvements
     - Vastly improved Xilinx flow
     - Added "make unsintall"

 * Equivalence checking
     - Added equivalence checking commands:
         equiv_make equiv_simple equiv_status
	 equiv_induct equiv_miter
	 equiv_add equiv_remove

 * Block RAM support:
     - Added "memory_bram" command
     - Added BRAM support to Xilinx flow

 * Other New Commands and Options
     - Added "dff2dffe"
     - Added "fsm -encfile"
     - Added "dfflibmap -prepare"
     - Added "write_blid -unbuf -undef -blackbox"
     - Added "write_smt2" for writing SMT-LIBv2 files
     - Added "test_cell -w -muxdiv"
     - Added "select -read"


Yosys 0.3.0 .. Yosys 0.4
------------------------

 * Platform Support
     - Added support for mxe-based cross-builds for win32
     - Added sourcecode-export as VisualStudio project
     - Added experimental EMCC (JavaScript) support

 * Verilog Frontend
     - Added -sv option for SystemVerilog (and automatic *.sv file support)
     - Added support for real-valued constants and constant expressions
     - Added support for non-standard "via_celltype" attribute on task/func
     - Added support for non-standard "module mod_name(...);" syntax
     - Added support for non-standard """ macro bodies
     - Added support for array with more than one dimension
     - Added support for $readmemh and $readmemb
     - Added support for DPI functions

 * Changes in internal cell library
     - Added $shift and $shiftx cell types
     - Added $alu, $lcu, $fa and $macc cell types
     - Removed $bu0 and $safe_pmux cell types
     - $mem/$memwr WR_EN input is now a per-data-bit enable signal
     - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
     - Renamed ports of $lut cells (from I->O to A->Y)
     - Renamed $_INV_ to $_NOT_

 * Changes for simple synthesis flows
     - There is now a "synth" command with a recommended default script
     - Many improvements in synthesis of arithmetic functions to gates
	 - Multipliers and adders with many operands are using carry-save adder trees
         - Remaining adders are now implemented using Brent-Kung carry look-ahead adders
     - Various new high-level optimizations on RTL netlist
     - Various improvements in FSM optimization
     - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)

 * Changes in internal APIs and RTLIL
     - Added log_id() and log_cell() helper functions
     - Added function-like cell creation helpers
     - Added GetSize() function (like .size() but with int)
     - Major refactoring of RTLIL::Module and related classes
     - Major refactoring of RTLIL::SigSpec and related classes
     - Now RTLIL::IdString is essentially an int
     - Added macros for code coverage counters
     - Added some Makefile magic for pretty make logs
     - Added "kernel/yosys.h" with all the core definitions
     - Changed a lot of code from FILE* to c++ streams
     - Added RTLIL::Monitor API and "trace" command
     - Added "Yosys" C++ namespace

 * Changes relevant to SAT solving
     - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
     - Added native ezSAT support for vector shift ops
     - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)

 * New commands (or large improvements to commands)
     - Added "synth" command with default script
     - Added "share" (finally some real resource sharing)
     - Added "memory_share" (reduce number of ports on memories)
     - Added "wreduce" and "alumacc" commands
     - Added "opt -keepdc -fine -full -fast"
     - Added some "test_*" commands

 * Various other changes
     - Added %D and %c select operators
     - Added support for labels in yosys scripts
     - Added support for here-documents in yosys scripts
     - Support "+/" prefix for files from proc_share_dir
     - Added "autoidx" statement to ilang language
     - Switched from "yosys-svgviewer" to "xdot"
     - Renamed "stdcells.v" to "techmap.v"
     - Various bug fixes and small improvements
     - Improved welcome and bye messages


Yosys 0.2.0 .. Yosys 0.3.0
--------------------------

 * Driver program and overall behavior:
     - Added "design -push" and "design -pop"
     - Added "tee" command for redirecting log output

 * Changes in the internal cell library:
     - Added $dlatchsr and $_DLATCHSR_???_ cell types

 * Improvements in Verilog frontend:
     - Improved support for const functions (case, always, repeat)
     - The generate..endgenerate keywords are now optional
     - Added support for arrays of module instances
     - Added support for "`default_nettype" directive
     - Added support for "`line" directive

 * Other front- and back-ends:
     - Various changes to "write_blif" options
     - Various improvements in EDIF backend
     - Added "vhdl2verilog" pseudo-front-end
     - Added "verific" pseudo-front-end

 * Improvements in technology mapping:
     - Added support for recursive techmap
     - Added CONSTMSK and CONSTVAL features to techmap
     - Added _TECHMAP_CONNMAP_*_ feature to techmap
     - Added _TECHMAP_REPLACE_ feature to techmap
     - Added "connwrappers" command for wrap-extract-unwrap method
     - Added "extract -map %<design_name>" feature
     - Added "extract -ignore_param ..." and "extract -ignore_parameters"
     - Added "techmap -max_iter" option

 * Improvements to "eval" and "sat" framework:
     - Now include a copy of Minisat (with build fixes applied)
     - Switched to Minisat::SimpSolver as SAT back-end
     - Added "sat -dump_vcd" feature
     - Added "sat -dump_cnf" feature
     - Added "sat -initsteps <N>" feature
     - Added "freduce -stop <N>" feature
     - Added "freduce -dump <prefix>" feature

 * Integration with ABC:
     - Updated ABC rev to 7600ffb9340c

 * Improvements in the internal APIs:
     - Added RTLIL::Module::add... helper methods
     - Various build fixes for OSX (Darwin) and OpenBSD


Yosys 0.1.0 .. Yosys 0.2.0
--------------------------

 * Changes to the driver program:
     - Added "yosys -h" and "yosys -H"
     - Added support for backslash line continuation in scripts
     - Added support for #-comments in same line as command
     - Added "echo" and "log" commands

 * Improvements in Verilog frontend:
     - Added support for local registers in named blocks
     - Added support for "case" in "generate" blocks
     - Added support for $clog2 system function
     - Added support for basic SystemVerilog assert statements
     - Added preprocessor support for macro arguments
     - Added preprocessor support for `elsif statement
     - Added "verilog_defaults" command
     - Added read_verilog -icells option
     - Added support for constant sizes from parameters
     - Added "read_verilog -setattr"
     - Added support for function returning 'integer'
     - Added limited support for function calls in parameter values
     - Added "read_verilog -defer" to suppress evaluation of modules with default parameters

 * Other front- and back-ends:
     - Added BTOR backend
     - Added Liberty frontend

 * Improvements in technology mapping:
     - The "dfflibmap" command now strongly prefers solutions with
           no inverters in clock paths
     - The "dfflibmap" command now prefers cells with smaller area
     - Added support for multiple -map options to techmap
     - Added "dfflibmap" support for //-comments in liberty files
     - Added "memory_unpack" command to revert "memory_collect"
     - Added standard techmap rule "techmap -share_map pmux2mux.v"
     - Added "iopadmap -bits"
     - Added "setundef" command
     - Added "hilomap" command

 * Changes in the internal cell library:
     - Major rewrite of simlib.v for better compatibility with other tools
     - Added PRIORITY parameter to $memwr cells
     - Added TRANSPARENT parameter to $memrd cells
     - Added RD_TRANSPARENT parameter to $mem cells
     - Added $bu0 cell (always 0-extend, even undef MSB)
     - Added $assert cell type
     - Added $slice and $concat cell types

 * Integration with ABC:
     - Updated ABC to hg rev 2058c8ccea68
     - Tighter integration of ABC build with Yosys build. The make
           targets 'make abc' and 'make install-abc' are now obsolete.
     - Added support for passing FFs from one clock domain through ABC
     - Now always use BLIF as exchange format with ABC
     - Added support for "abc -script +<command_sequence>"
     - Improved standard ABC recipe
     - Added support for "keep" attribute to abc command
     - Added "abc -dff / -clk / -keepff" options

 * Improvements to "eval" and "sat" framework:
     - Added support for "0" and "~0" in right-hand side -set expressions
     - Added "eval -set-undef" and "eval -table"
     - Added "sat -set-init" and "sat -set-init-*" for sequential problems
     - Added undef support to SAT solver, incl. various new "sat" options
     - Added correct support for === and !== for "eval" and "sat"
     - Added "sat -tempinduct" (default -seq is now non-induction sequential)
     - Added "sat -prove-asserts"
     - Complete rewrite of the 'freduce' command
     - Added "miter" command
     - Added "sat -show-inputs" and "sat -show-outputs"
     - Added "sat -ignore_unknown_cells" (now produce an error by default)
     - Added "sat -falsify"
     - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
     - Added "expose" command
     - Added support for @<sel_name> to sat and eval signal expressions

 * Changes in the 'make test' framework and auxiliary test tools:
     - Added autotest.sh -p and -f options
     - Replaced autotest.sh ISIM support with XSIM support
     - Added test cases for SAT framework

 * Added "abbreviated IDs":
     - Now $<something>$foo can be abbreviated as $foo.
     - Usually this last part is a unique id (from RTLIL::autoidx)
     - This abbreviated IDs are now also used in "show" output

 * Other changes to selection framework:
     - Now */ is optional in */<mode>:<arg> expressions
     - Added "select -assert-none" and "select -assert-any"
     - Added support for matching modules by attribute (A:<expr>)
     - Added "select -none"
     - Added support for r:<expr> pattern for matching cell parameters
     - Added support for !=, <, <=, >=, > for attribute and parameter matching
     - Added support for %s for selecting sub-modules
     - Added support for %m for expanding selections to whole modules
     - Added support for i:*, o:* and x:* pattern for selecting module ports
     - Added support for s:<expr> pattern for matching wire width
     - Added support for %a operation to select wire aliases

 * Various other changes to commands and options:
     - The "ls" command now supports wildcards
     - Added "show -pause" and "show -format dot"
     - Added "show -color" support for cells
     - Added "show -label" and "show -notitle"
     - Added "dump -m" and "dump -n"
     - Added "history" command
     - Added "rename -hide"
     - Added "connect" command
     - Added "splitnets -driver"
     - Added "opt_const -mux_undef"
     - Added "opt_const -mux_bool"
     - Added "opt_const -undriven"
     - Added "opt -mux_undef -mux_bool -undriven -purge"
     - Added "hierarchy -libdir"
     - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
     - Added "delete" command
     - Added "dump -append"
     - Added "setattr" and "setparam" commands
     - Added "design -stash/-copy-from/-copy-to"
     - Added "copy" command
     - Added "splice" command