meta: move all ISLE-related generated code to cranelift-codegen-meta (bytecodealliance#10352)

* meta: move all ISLE-related generated code to `cranelift-codegen-meta`

Previously, the new `cranelift-assembler-x64` crate would generate the
assembler Rust code, the ISLE integration code, and the ISLE's
accompanying Rust macro all in the same crate. Because these last two
files were generated in the assembler's `OUT_DIR`, they caused issues
for deterministic builds that expect those files in
`cranelift-codegen`'s `OUT_DIR` (see bytecodealliance#10348). This change fixes that by
moving all of the assembler's generated integration code, the ISLE
instruction definitions and their accompanying Rust macro, to the
`cranelift-codegen-meta` crate.

This has the added advantage that `cranelift-assembler-x64` now can
focus exclusively on being an assembler and not being concerned with the
ISLE integration, which is substantial.

* Move lint `allow` to problem site

Apparently allowing unused variables for unimplemented parts of fixed
register instructions will not work at the macro scope; this moves the
`allow` to the offending line.

* Remove `rustfmt` of generated assembler code

Author: abrown

Cargo.lock

@@ -9,11 +9,7 @@ fn main() {
 
     let out_dir = env::var("OUT_DIR").expect("The OUT_DIR environment variable must be set");
     let out_dir = Path::new(&out_dir);
-    let built_files = [
-        meta::generate_rust_assembler(out_dir, "assembler.rs"),
-        meta::generate_isle_macro(out_dir, "assembler-isle-macro.rs"),
-        meta::generate_isle_definitions(out_dir, "assembler-definitions.isle"),
-    ];
+    let built_files = [meta::generate_rust_assembler(out_dir, "assembler.rs")];
 
     // Generating this additional bit of Rust is necessary for listing the
     // generated files.

cranelift/assembler-x64/build.rs

@@ -31,63 +31,6 @@ pub fn rust_assembler(f: &mut Formatter, insts: &[dsl::Inst]) {
     dsl::Feature::generate_enum(f);
 }
 
-/// Generate the `isle_assembler_methods!` macro.
-pub fn isle_macro(f: &mut Formatter, insts: &[dsl::Inst]) {
-    fmtln!(f, "#[macro_export]");
-    fmtln!(f, "macro_rules! isle_assembler_methods {{");
-    f.indent(|f| {
-        fmtln!(f, "() => {{");
-        f.indent(|f| {
-            for inst in insts {
-                inst.generate_isle_macro(f);
-            }
-        });
-        fmtln!(f, "}};");
-    });
-    fmtln!(f, "}}");
-}
-
-/// Generate the ISLE definitions that match the `isle_assembler_methods!` macro
-/// above.
-pub fn isle_definitions(f: &mut Formatter, insts: &[dsl::Inst]) {
-    fmtln!(f, "(type AssemblerOutputs (enum");
-    fmtln!(f, "    ;; Used for instructions that have ISLE `SideEffect`s (memory stores, traps,");
-    fmtln!(f, "    ;; etc.) and do not return a `Value`.");
-    fmtln!(f, "    (SideEffect (inst MInst))");
-    fmtln!(f, "    ;; Used for instructions that return a GPR (including `GprMem` variants with");
-    fmtln!(f, "    ;; a GPR as the first argument).");
-    fmtln!(f, "    (RetGpr (inst MInst) (gpr Gpr))");
-    fmtln!(f, "    ;; Used for instructions that return an XMM register.");
-    fmtln!(f, "    (RetXmm (inst MInst) (xmm Xmm))");
-    fmtln!(f, "    ;; TODO: eventually add more variants for multi-return, XMM, etc.; see");
-    fmtln!(f, "    ;; https://github.com/bytecodealliance/wasmtime/pull/10276");
-    fmtln!(f, "))");
-    f.empty_line();
-
-    fmtln!(f, ";; Directly emit instructions that return a GPR.");
-    fmtln!(f, "(decl emit_ret_gpr (AssemblerOutputs) Gpr)");
-    fmtln!(f, "(rule (emit_ret_gpr (AssemblerOutputs.RetGpr inst gpr))");
-    fmtln!(f, "    (let ((_ Unit (emit inst))) gpr))");
-    f.empty_line();
-
-    fmtln!(f, ";; Directly emit instructions that return an XMM register.");
-    fmtln!(f, "(decl emit_ret_xmm (AssemblerOutputs) Xmm)");
-    fmtln!(f, "(rule (emit_ret_xmm (AssemblerOutputs.RetXmm inst xmm))");
-    fmtln!(f, "    (let ((_ Unit (emit inst))) xmm))");
-    f.empty_line();
-
-    fmtln!(f, ";; Pass along the side-effecting instruction for later emission.");
-    fmtln!(f, "(decl defer_side_effect (AssemblerOutputs) SideEffectNoResult)");
-    fmtln!(f, "(rule (defer_side_effect (AssemblerOutputs.SideEffect inst))");
-    fmtln!(f, "    (SideEffectNoResult.Inst inst))");
-    f.empty_line();
-
-    for inst in insts {
-        inst.generate_isle_definition(f);
-        f.empty_line();
-    }
-}
-
 /// `enum Inst { ... }`
 fn generate_inst_enum(f: &mut Formatter, insts: &[dsl::Inst]) {
     fmtln!(f, "#[doc(hidden)]");

cranelift/assembler-x64/meta/src/generate.rs

@@ -3,7 +3,6 @@
 
 use super::{fmtln, Formatter};
 use crate::dsl;
-use crate::generate::inst::IsleConstructor;
 
 impl dsl::Format {
     /// Re-order the Intel-style operand order to accommodate ATT-style
@@ -226,45 +225,6 @@ impl dsl::Format {
             }
         }
     }
-
-    /// Returns the ISLE constructors that are going to be used when generating
-    /// this instruction.
-    ///
-    /// Note that one instruction might need multiple constructors, such as one
-    /// for operating on memory and one for operating on registers.
-    pub fn isle_constructors(&self) -> Vec<IsleConstructor> {
-        use dsl::Mutability::*;
-        use dsl::OperandKind::*;
-
-        let write_operands = self
-            .operands
-            .iter()
-            .filter(|o| o.mutability.is_write())
-            .collect::<Vec<_>>();
-        match &write_operands[..] {
-            [] => unimplemented!("if you truly need this (and not a `SideEffect*`), add a `NoReturn` variant to `AssemblerOutputs`"),
-            [one] => match one.mutability {
-                Read => unreachable!(),
-                ReadWrite => match one.location.kind() {
-                    Imm(_) => unreachable!(),
-                    FixedReg(_) => vec![IsleConstructor::RetGpr],
-                    // One read/write register output? Output the instruction
-                    // and that register.
-                    Reg(r) => match r.bits() {
-                        128 => vec![IsleConstructor::RetXmm],
-                        _ => vec![IsleConstructor::RetGpr],
-                    },
-                    // One read/write reg-mem output? We need constructors for
-                    // both variants.
-                    RegMem(rm) => match rm.bits() {
-                        128 => vec![IsleConstructor::RetXmm, IsleConstructor::RetMemorySideEffect],
-                        _ => vec![IsleConstructor::RetGpr, IsleConstructor::RetMemorySideEffect],
-                    },
-                }
-            },
-            other => panic!("unsupported number of write operands {other:?}"),
-        }
-    }
 }
 
 impl dsl::Rex {

cranelift/assembler-x64/meta/src/generate/format.rs

@@ -1,6 +1,5 @@
 use super::{fmtln, generate_derive, generate_derive_arbitrary_bounds, Formatter};
 use crate::dsl;
-use crate::dsl::OperandKind;
 
 impl dsl::Inst {
     /// `struct <inst> { <op>: Reg, <op>: Reg, ... }`
@@ -229,240 +228,8 @@ impl dsl::Inst {
             });
         });
     }
-
-    /// `fn x64_<inst>(&mut self, <params>) -> Inst<R> { ... }`
-    ///
-    /// # Panics
-    ///
-    /// This function panics if the instruction has no operands.
-    pub fn generate_isle_macro(&self, f: &mut Formatter) {
-        let struct_name = self.name();
-        let params = self
-            .format
-            .operands
-            .iter()
-            .filter(|o| o.mutability.is_read())
-            // FIXME(#10238) don't filter out fixed regs here
-            .filter(|o| !matches!(o.location.kind(), OperandKind::FixedReg(_)))
-            .collect::<Vec<_>>();
-        let results = self
-            .format
-            .operands
-            .iter()
-            .filter(|o| o.mutability.is_write())
-            .collect::<Vec<_>>();
-        let rust_params = params
-            .iter()
-            .map(|o| format!("{}: {}", o.location, o.rust_param_raw()))
-            .collect::<Vec<_>>()
-            .join(", ");
-        f.add_block(
-            &format!("fn x64_{struct_name}_raw(&mut self, {rust_params}) -> AssemblerOutputs"),
-            |f| {
-                for o in params.iter() {
-                    let l = o.location;
-                    match o.rust_convert_isle_to_assembler() {
-                        Some(cvt) => fmtln!(f, "let {l} = {cvt}({l});"),
-                        None => fmtln!(f, "let {l} = {l}.clone();"),
-                    }
-                }
-                let args = params
-                    .iter()
-                    .map(|o| format!("{}.clone()", o.location))
-                    .collect::<Vec<_>>();
-                let args = args.join(", ");
-                fmtln!(f, "let inst = cranelift_assembler_x64::inst::{struct_name}::new({args}).into();");
-                fmtln!(f, "let inst = MInst::External {{ inst }};");
-
-                use dsl::Mutability::*;
-                match results.as_slice() {
-                    [] => fmtln!(f, "SideEffectNoResult::Inst(inst)"),
-                    [one] => match one.mutability {
-                        Read => unreachable!(),
-                        ReadWrite => match one.location.kind() {
-                            OperandKind::Imm(_) => unreachable!(),
-                            // FIXME(#10238)
-                            OperandKind::FixedReg(_) => fmtln!(f, "todo!()"),
-                            // One read/write register output? Output the instruction
-                            // and that register.
-                            OperandKind::Reg(r) => match r.bits() {
-                                128 => {
-                                    fmtln!(f, "let xmm = {}.as_ref().write.to_reg();", results[0].location);
-                                    fmtln!(f, "AssemblerOutputs::RetXmm {{ inst, xmm }}")
-                                }
-                                _ => {
-                                    fmtln!(f, "let gpr = {}.as_ref().write.to_reg();", results[0].location);
-                                    fmtln!(f, "AssemblerOutputs::RetGpr {{ inst, gpr }}")
-                                }
-                            },
-                            // One read/write regmem output? We need to output
-                            // everything and it'll internally disambiguate which was
-                            // emitted (e.g. the mem variant or the register variant).
-                            OperandKind::RegMem(_) => {
-                                assert_eq!(results.len(), 1);
-                                let l = results[0].location;
-                                f.add_block(&format!("match {l}"), |f| match l.bits() {
-                                    128 => {
-                                        f.add_block("asm::XmmMem::Xmm(reg) => ", |f| {
-                                            fmtln!(f, "let xmm = reg.write.to_reg();");
-                                            fmtln!(f, "AssemblerOutputs::RetXmm {{ inst, xmm }} ");
-                                        });
-                                        f.add_block("asm::XmmMem::Mem(_) => ", |f| {
-                                            fmtln!(f, "AssemblerOutputs::SideEffect {{ inst }} ");
-                                        });
-                                    }
-                                    _ => {
-                                        f.add_block("asm::GprMem::Gpr(reg) => ", |f| {
-                                            fmtln!(f, "let gpr = reg.write.to_reg();");
-                                            fmtln!(f, "AssemblerOutputs::RetGpr {{ inst, gpr }} ")
-                                        });
-                                        f.add_block("asm::GprMem::Mem(_) => ", |f| {
-                                            fmtln!(f, "AssemblerOutputs::SideEffect {{ inst }} ");
-                                        });
-                                    }
-                                });
-                            }
-                        },
-                    },
-                    _ => panic!("instruction has more than one result"),
-                }
-            },
-        );
-    }
-
-    /// Generate a "raw" constructor that simply constructs, but does not emit
-    /// the assembly instruction:
-    ///
-    /// ```text
-    /// (decl x64_<inst>_raw (<params>) AssemblerOutputs)
-    /// (extern constructor x64_<inst>_raw x64_<inst>_raw)
-    /// ```
-    ///
-    /// Using the "raw" constructor, we also generate "emitter" constructors
-    /// (see [`IsleConstructor`]). E.g., instructions that write to a register
-    /// will return the register:
-    ///
-    /// ```text
-    /// (decl x64_<inst> (<params>) Gpr)
-    /// (rule (x64_<inst> <params>) (emit_ret_gpr (x64_<inst>_raw <params>)))
-    /// ```
-    ///
-    /// For instructions that write to memory, we also generate an "emitter"
-    /// constructor with the `_mem` suffix:
-    ///
-    /// ```text
-    /// (decl x64_<inst>_mem (<params>) SideEffectNoResult)
-    /// (rule (x64_<inst>_mem <params>) (defer_side_effect (x64_<inst>_raw <params>)))
-    /// ```
-    ///
-    /// # Panics
-    ///
-    /// This function panics if the instruction has no operands.
-    pub fn generate_isle_definition(&self, f: &mut Formatter) {
-        // First declare the "raw" constructor which is implemented in Rust
-        // with `generate_isle_macro` above. This is an "extern" constructor
-        // with relatively raw types. This is not intended to be used by
-        // general lowering rules in ISLE.
-        let struct_name = self.name();
-        let raw_name = format!("x64_{struct_name}_raw");
-        let params = self
-            .format
-            .operands
-            .iter()
-            .filter(|o| o.mutability.is_read())
-            // FIXME(#10238) don't filter out fixed regs here
-            .filter(|o| !matches!(o.location.kind(), OperandKind::FixedReg(_)))
-            .collect::<Vec<_>>();
-        let raw_param_tys = params
-            .iter()
-            .map(|o| o.isle_param_raw())
-            .collect::<Vec<_>>()
-            .join(" ");
-        fmtln!(f, "(decl {raw_name} ({raw_param_tys}) AssemblerOutputs)");
-        fmtln!(f, "(extern constructor {raw_name} {raw_name})");
-
-        // Next, for each "emitter" ISLE constructor being generated, synthesize
-        // a pure-ISLE constructor which delegates appropriately to the `*_raw`
-        // constructor above.
-        //
-        // The main purpose of these constructors is to have faithful type
-        // signatures for the SSA nature of VCode/ISLE, effectively translating
-        // x64's type system to ISLE/VCode's type system.
-        for ctor in self.format.isle_constructors() {
-            let suffix = ctor.suffix();
-            let rule_name = format!("x64_{struct_name}{suffix}");
-            let result_ty = ctor.result_ty();
-            let param_tys = params
-                .iter()
-                .map(|o| o.isle_param_for_ctor(ctor))
-                .collect::<Vec<_>>()
-                .join(" ");
-            let param_names = params
-                .iter()
-                .map(|o| o.location.to_string())
-                .collect::<Vec<_>>()
-                .join(" ");
-            let convert = ctor.conversion_constructor();
-
-            fmtln!(f, "(decl {rule_name} ({param_tys}) {result_ty})");
-            fmtln!(f, "(rule ({rule_name} {param_names}) ({convert} ({raw_name} {param_names})))");
-        }
-    }
 }
 
 fn comma_join<I: Into<String>>(items: impl Iterator<Item = I>) -> String {
     items.map(Into::into).collect::<Vec<_>>().join(", ")
 }
-
-/// Different kinds of ISLE constructors generated for a particular instruction.
-///
-/// One instruction may generate a single constructor or multiple constructors.
-/// For example an instruction that writes its result to a register will
-/// generate only a single constructor. An instruction where the destination
-/// read/write operand is `GprMem` will generate two constructors though, one
-/// for memory and one for in registers.
-#[derive(Copy, Clone, Debug)]
-pub enum IsleConstructor {
-    /// This constructor only produces a side effect, meaning that the
-    /// instruction does not produce results in registers. This may produce
-    /// a result in memory, however.
-    RetMemorySideEffect,
-
-    /// This constructor produces a `Gpr` value, meaning that it will write the
-    /// result to a `Gpr`.
-    RetGpr,
-
-    /// This constructor produces an `Xmm` value, meaning that it will write the
-    /// result to an `Xmm`.
-    RetXmm,
-}
-
-impl IsleConstructor {
-    /// Returns the result type, in ISLE, that this constructor generates.
-    pub fn result_ty(&self) -> &'static str {
-        match self {
-            IsleConstructor::RetMemorySideEffect => "SideEffectNoResult",
-            IsleConstructor::RetGpr => "Gpr",
-            IsleConstructor::RetXmm => "Xmm",
-        }
-    }
-
-    /// Returns the constructor used to convert an `AssemblerOutput` into the
-    /// type returned by [`Self::result_ty`].
-    pub fn conversion_constructor(&self) -> &'static str {
-        match self {
-            IsleConstructor::RetMemorySideEffect => "defer_side_effect",
-            IsleConstructor::RetGpr => "emit_ret_gpr",
-            IsleConstructor::RetXmm => "emit_ret_xmm",
-        }
-    }
-
-    /// Returns the suffix used in the ISLE constructor name.
-    pub fn suffix(&self) -> &'static str {
-        match self {
-            IsleConstructor::RetMemorySideEffect => "_mem",
-            IsleConstructor::RetGpr => "",
-            IsleConstructor::RetXmm => "",
-        }
-    }
-}