@@ -661,6 +661,60 @@ static const struct pios_usart_cfg pios_uart4_cfg = {
661661 },
662662};
663663
664+ /*
665+ USART6 DMA config.
666+ */
667+ static struct pios_usart_dma_cfg pios_usart6_dma_rx_cfg = {
668+ .stream = DMA2_Stream2 ,
669+ .tcif = DMA_FLAG_TCIF2 ,
670+ .init = {
671+ /* Could probably thin out some of these, that are defined to zero anyway. */
672+ .DMA_Channel = DMA_Channel_5 ,
673+ .DMA_PeripheralBaseAddr = (uint32_t )& USART6 -> DR ,
674+ .DMA_MemoryDataSize = DMA_MemoryDataSize_Byte ,
675+ .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte ,
676+ .DMA_MemoryInc = DMA_MemoryInc_Enable ,
677+ .DMA_PeripheralInc = DMA_PeripheralInc_Disable ,
678+ .DMA_DIR = DMA_DIR_PeripheralToMemory ,
679+ .DMA_Mode = DMA_Mode_Normal ,
680+ .DMA_Priority = DMA_Priority_High ,
681+ .DMA_MemoryBurst = DMA_MemoryBurst_Single ,
682+ .DMA_PeripheralBurst = DMA_PeripheralBurst_Single ,
683+ .DMA_FIFOMode = DMA_FIFOMode_Disable ,
684+ },
685+ .irq = {
686+ .NVIC_IRQChannel = DMA2_Stream2_IRQn ,
687+ .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_LOW ,
688+ .NVIC_IRQChannelSubPriority = 0 ,
689+ .NVIC_IRQChannelCmd = ENABLE ,
690+ }
691+ };
692+ static struct pios_usart_dma_cfg pios_usart6_dma_tx_cfg = {
693+ .stream = DMA2_Stream7 ,
694+ .tcif = DMA_FLAG_TCIF7 ,
695+ .init = {
696+ /* Could probably thin out some of these, that are defined to zero anyway. */
697+ .DMA_Channel = DMA_Channel_5 ,
698+ .DMA_PeripheralBaseAddr = (uint32_t )& USART6 -> DR ,
699+ .DMA_MemoryDataSize = DMA_MemoryDataSize_Byte ,
700+ .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte ,
701+ .DMA_MemoryInc = DMA_MemoryInc_Enable ,
702+ .DMA_PeripheralInc = DMA_PeripheralInc_Disable ,
703+ .DMA_DIR = DMA_DIR_MemoryToPeripheral ,
704+ .DMA_Mode = DMA_Mode_Normal ,
705+ .DMA_Priority = DMA_Priority_High ,
706+ .DMA_MemoryBurst = DMA_MemoryBurst_Single ,
707+ .DMA_PeripheralBurst = DMA_PeripheralBurst_Single ,
708+ .DMA_FIFOMode = DMA_FIFOMode_Disable ,
709+ },
710+ .irq = {
711+ .NVIC_IRQChannel = DMA2_Stream7_IRQn ,
712+ .NVIC_IRQChannelPreemptionPriority = PIOS_IRQ_PRIO_LOW ,
713+ .NVIC_IRQChannelSubPriority = 0 ,
714+ .NVIC_IRQChannelCmd = ENABLE ,
715+ }
716+ };
717+
664718static const struct pios_usart_cfg pios_usart6_cfg = {
665719 .regs = USART6 ,
666720 .remap = GPIO_AF_USART6 ,
@@ -694,8 +748,19 @@ static const struct pios_usart_cfg pios_usart6_cfg = {
694748 },
695749 .pin_source = GPIO_PinSource6 ,
696750 },
751+ .dma_recv = & pios_usart6_dma_rx_cfg ,
752+ .dma_send = & pios_usart6_dma_tx_cfg
697753};
698754
755+ void DMA2_Stream2_IRQHandler (void )
756+ {
757+ PIOS_USART_dma_irq_rx_handler (& pios_usart6_cfg );
758+ }
759+ void DMA2_Stream7_IRQHandler (void )
760+ {
761+ PIOS_USART_dma_irq_tx_handler (& pios_usart6_cfg );
762+ }
763+
699764#endif /* PIOS_INCLUDE_USART */
700765
701766#if defined(PIOS_INCLUDE_COM )
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