feat(lvgl_port_simd): Support for esp32s2, assembly rendering#559
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feat(lvgl_port_simd): Support for esp32s2, assembly rendering#559peter-marcisovsky wants to merge 1 commit intomasterfrom
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Test Results 19 files 19 suites 6m 18s ⏱️ Results for commit 3df2792. ♻️ This comment has been updated with latest results. |
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2 tasks
- renamed assembly src files to xtensa_pie, xtensa_base
- xtensa_base src files use zero-overhead loops only for esp32
- added zero length matrix check into all src files
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This MR enables esp32s2 for assembly rendering.
esp32s2 differs from esp32 a little in terms of ISA, the most significant difference here is missing zero-overhead loops (
loopnezinstruction) on esp32s2, which is used in each assembly cycle on esp32 (esp32s3).loopnezcan be omitted for esp32s2 using branching loops (which are little less efficient than the zero-overhead loops).Changes:
.._esp32.S.._esp32s3.Sto.._xtensa_base.S.._xtensa_pie.SESP-BSP Pull Request checklist
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