Skip to content

Commit dcdec1c

Browse files
committed
Rename Tx/Rx futures to Write/Read
Tx as "transfer" was being overloaded with "DMA transfer," which we're using to mean the entire DMA operation. Receive was fine, but pairing it with its best antonym, "Send," didn't seem right; Send means something else in Rust. Read and write should be just as clear as to the DMA action that's happening.
1 parent 6720d2f commit dcdec1c

4 files changed

Lines changed: 30 additions & 30 deletions

File tree

examples/teensy4/src/bin/uart.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -189,14 +189,14 @@ fn main() -> ! {
189189

190190
loop {
191191
let mut buffer = [0u8; 1];
192-
let receive = imxrt_dma::peripheral::receive(&mut channel, &mut uart, &mut buffer);
193-
assert!(support::wfi(receive).is_ok());
192+
let read = imxrt_dma::peripheral::read(&mut channel, &mut uart, &mut buffer);
193+
assert!(support::wfi(read).is_ok());
194194

195195
log::info!("Received a byte: {}", buffer[0]);
196196

197197
let buffer = [buffer[0]; 32];
198-
let transfer = imxrt_dma::peripheral::transfer(&mut channel, &buffer, &mut uart);
199-
assert!(support::wfi(transfer).is_ok());
198+
let write = imxrt_dma::peripheral::write(&mut channel, &buffer, &mut uart);
199+
assert!(support::wfi(write).is_ok());
200200

201201
log::info!("Replied!");
202202
systick.delay(1);

src/interrupt.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -92,8 +92,8 @@ pub(crate) const NO_WAKER: SharedWaker = Mutex::new(RefCell::new(None));
9292
/// using
9393
///
9494
/// - [`Memcpy`](crate::memcpy::Memcpy) for buffer-to-buffer DMA transfers
95-
/// - [`Rx`](crate::peripheral::Rx) for peripheral-to-memory DMA transfers
96-
/// - [`Tx`](crate::peripheral::Tx) for memory-to-peripheral DMA transfers
95+
/// - [`Read`](crate::peripheral::Read) for peripheral-to-memory DMA transfers
96+
/// - [`Write`](crate::peripheral::Write) for memory-to-peripheral DMA transfers
9797
///
9898
/// `Transfer` is designed to the DMA `Channel` public interface. If you need to implement
9999
/// your own transfer future, you may do so.

src/lib.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,9 +40,9 @@
4040
//! Once you have a channel, you can use the higher-level DMA APIs, like
4141
//!
4242
//! - [`memcpy`](crate::memcpy::memcpy) for memory copies.
43-
//! - [`transfer`](crate::peripheral::transfer) to transmit data from memory to
43+
//! - [`write`](crate::peripheral::write) to transmit data from memory to
4444
//! a peripheral.
45-
//! - [`receive`](crate::peripheral::receive) to receive data from a peripheral.
45+
//! - [`read`](crate::peripheral::read) to receive data from a peripheral.
4646
//! - [`full_duplex`](crate::peripheral::full_duplex) to read / write with a
4747
//! peripheral using a single buffer.
4848
//!

src/peripheral.rs

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -95,9 +95,9 @@ pub unsafe trait Destination<E: Element> {
9595
/// A DMA transfer that receives data from hardware
9696
///
9797
/// The future resolves when the peripheral has provided all
98-
/// expected data. Use [`receive()`](crate::peripheral::receive) to construct
98+
/// expected data. Use [`read()`](crate::peripheral::read) to construct
9999
/// this future.
100-
pub struct Rx<'a, S, E>
100+
pub struct Read<'a, S, E>
101101
where
102102
S: Source<E>,
103103
E: Element,
@@ -108,7 +108,7 @@ where
108108
_elem: PhantomData<&'a mut E>,
109109
}
110110

111-
impl<S, E> Future for Rx<'_, S, E>
111+
impl<S, E> Future for Read<'_, S, E>
112112
where
113113
S: Source<E>,
114114
E: Element,
@@ -120,7 +120,7 @@ where
120120
}
121121
}
122122

123-
impl<S, E> Drop for Rx<'_, S, E>
123+
impl<S, E> Drop for Read<'_, S, E>
124124
where
125125
S: Source<E>,
126126
E: Element,
@@ -132,7 +132,7 @@ where
132132
}
133133
}
134134

135-
fn prepare_receive<S, E>(channel: &mut Channel, source: &mut S, buffer: &mut [E])
135+
fn prepare_read<S, E>(channel: &mut Channel, source: &mut S, buffer: &mut [E])
136136
where
137137
S: Source<E>,
138138
E: Element,
@@ -191,24 +191,24 @@ where
191191
///
192192
/// let mut buffer = [0u8; 32];
193193
///
194-
/// peripheral::receive(
194+
/// peripheral::read(
195195
/// &mut channel_7,
196196
/// &mut lpuart,
197197
/// &mut buffer,
198198
/// ).await?;
199199
/// # Ok(()) }
200200
/// ```
201-
pub fn receive<'a, S, E>(
201+
pub fn read<'a, S, E>(
202202
channel: &'a mut Channel,
203203
source: &'a mut S,
204204
buffer: &'a mut [E],
205-
) -> Rx<'a, S, E>
205+
) -> Read<'a, S, E>
206206
where
207207
S: Source<E>,
208208
E: Element,
209209
{
210-
prepare_receive(channel, source, buffer);
211-
Rx {
210+
prepare_read(channel, source, buffer);
211+
Read {
212212
channel,
213213
// Safety: transfer is correctly defined
214214
transfer: unsafe { Transfer::new(channel) },
@@ -220,8 +220,8 @@ where
220220
/// A DMA transfer that sends data to hardware
221221
///
222222
/// The future resolves when the device has sent all provided data.
223-
/// Use [`transfer()`](crate::peripheral::transfer) to construct this future.
224-
pub struct Tx<'a, D, E>
223+
/// Use [`write()`](crate::peripheral::write) to construct this future.
224+
pub struct Write<'a, D, E>
225225
where
226226
D: Destination<E>,
227227
E: Element,
@@ -232,7 +232,7 @@ where
232232
_elem: PhantomData<&'a E>,
233233
}
234234

235-
impl<D, E> Future for Tx<'_, D, E>
235+
impl<D, E> Future for Write<'_, D, E>
236236
where
237237
D: Destination<E>,
238238
E: Element,
@@ -244,7 +244,7 @@ where
244244
}
245245
}
246246

247-
impl<D, E> Drop for Tx<'_, D, E>
247+
impl<D, E> Drop for Write<'_, D, E>
248248
where
249249
D: Destination<E>,
250250
E: Element,
@@ -256,7 +256,7 @@ where
256256
}
257257
}
258258

259-
fn prepare_transfer<D, E>(channel: &mut Channel, buffer: &[E], destination: &mut D)
259+
fn prepare_write<D, E>(channel: &mut Channel, buffer: &[E], destination: &mut D)
260260
where
261261
D: Destination<E>,
262262
E: Element,
@@ -315,24 +315,24 @@ where
315315
///
316316
/// let buffer = [4u8, 5, 6, 7, 8];
317317
///
318-
/// peripheral::transfer(
318+
/// peripheral::write(
319319
/// &mut channel_7,
320320
/// &buffer,
321321
/// &mut lpuart,
322322
/// ).await?;
323323
/// # Ok(()) }
324324
/// ```
325-
pub fn transfer<'a, D, E>(
325+
pub fn write<'a, D, E>(
326326
channel: &'a mut Channel,
327327
buffer: &'a [E],
328328
destination: &'a mut D,
329-
) -> Tx<'a, D, E>
329+
) -> Write<'a, D, E>
330330
where
331331
D: Destination<E>,
332332
E: Element,
333333
{
334-
prepare_transfer(channel, buffer, destination);
335-
Tx {
334+
prepare_write(channel, buffer, destination);
335+
Write {
336336
channel,
337337
destination,
338338
// Safety: transfer is correctly defined
@@ -447,8 +447,8 @@ where
447447
P: Bidirectional<E>,
448448
E: Element,
449449
{
450-
prepare_transfer(tx_channel, buffer, peripheral);
451-
prepare_receive(rx_channel, peripheral, buffer);
450+
prepare_write(tx_channel, buffer, peripheral);
451+
prepare_read(rx_channel, peripheral, buffer);
452452

453453
FullDuplex {
454454
rx_channel,

0 commit comments

Comments
 (0)