Upgrade to Rust 2024 throughout workspace

mciantyre · mciantyre · commit d6fb13b0d825 · 2026-04-12T16:13:05.000-04:00
Includes a combination of formatting changes and fixes for the new
edition.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -67,6 +67,8 @@ are still exposed when building with a chip feature.
 **BREAKING** Remove the `timer` module, including most embedded-hal 0.2 blocking
 delay implementations.
 
+**BREAKING** Upgrade to Rust 2024.
+
 Introduce an `imxrt1180` feature to support the RT1180 series.
 
 Add a `defmt` feature targeting version 0.3. When enabled, select imxrt-hal
diff --git a/Cargo.toml b/Cargo.toml
@@ -118,7 +118,7 @@ repository = "https://github.com/imxrt-rs/imxrt-hal"
 keywords = ["imxrt", "nxp", "embedded", "no_std", "embedded-hal"]
 categories = ["embedded", "no-std"]
 license = "MIT OR Apache-2.0"
-edition = "2021"
+edition = "2024"
 
 [profile.dev]
 opt-level = 1
diff --git a/board/src/imxrt1010evk.rs b/board/src/imxrt1010evk.rs
@@ -300,9 +300,9 @@ pub(crate) const CLOCK_GATES: &[clock_gate::Locator] = &[
 /// set alternates here.
 fn configure_pins(
     super::Pads {
-        ref mut gpio,
-        ref mut gpio_sd,
-        ref mut gpio_ad,
+        gpio,
+        gpio_sd,
+        gpio_ad,
         ..
     }: &mut super::Pads,
 ) {
diff --git a/board/src/imxrt1060evk.rs b/board/src/imxrt1060evk.rs
@@ -255,8 +255,8 @@ pub(crate) const CLOCK_GATES: &[clock_gate::Locator] = &[
 /// set alternates here.
 fn configure_pins(
     super::Pads {
-        ref mut gpio_ad_b1,
-        ref mut gpio_sd_b0,
+        gpio_ad_b1,
+        gpio_sd_b0,
         ..
     }: &mut super::Pads,
 ) {
diff --git a/board/src/imxrt10xx/clock.rs b/board/src/imxrt10xx/clock.rs
@@ -6,17 +6,17 @@
 //! API, so we'll revisit this separation later.
 
 use super::clock_tree;
-use crate::{board_impl, hal, ral, GPT1_DIVIDER, GPT2_DIVIDER, RUN_MODE};
+use crate::{GPT1_DIVIDER, GPT2_DIVIDER, RUN_MODE, board_impl, hal, ral};
 
 /// Configure board clocks and power.
 ///
 /// # Safety
 ///
 /// Pokes at MMIO. Should only be done once.
 pub(crate) unsafe fn configure() {
-    let mut ccm = ral::ccm::CCM::instance();
-    let mut ccm_analog = ral::ccm_analog::CCM_ANALOG::instance();
-    let mut dcdc = ral::dcdc::DCDC::instance();
+    let mut ccm = unsafe { ral::ccm::CCM::instance() };
+    let mut ccm_analog = unsafe { ral::ccm_analog::CCM_ANALOG::instance() };
+    let mut dcdc = unsafe { ral::dcdc::DCDC::instance() };
 
     hal::ccm::set_low_power_mode(&mut ccm, hal::ccm::LowPowerMode::RemainInRun);
     super::power::set_target_power(&mut dcdc, RUN_MODE);
diff --git a/board/src/imxrt10xx/clock_tree.rs b/board/src/imxrt10xx/clock_tree.rs
@@ -12,11 +12,11 @@
 
 pub(crate) use super::ahb::{ahb_frequency, configure_ahb_ipg};
 use crate::{
+    RunMode,
     hal::ccm::{
-        analog, clock_gate, lpi2c_clk, lpspi_clk, perclk_clk, sai_clk, uart_clk, XTAL_OSCILLATOR_HZ,
+        XTAL_OSCILLATOR_HZ, analog, clock_gate, lpi2c_clk, lpspi_clk, perclk_clk, sai_clk, uart_clk,
     },
     ral::ccm::CCM,
-    RunMode,
 };
 
 pub(crate) const fn ipg_divider(run_mode: RunMode) -> u32 {
diff --git a/board/src/imxrt10xx/clock_tree/pll1_ahb.rs b/board/src/imxrt10xx/clock_tree/pll1_ahb.rs
@@ -3,7 +3,7 @@
 //! It supports the 1060. It should also support the 1050.
 
 use crate::ral;
-use crate::{hal::ccm, RunMode};
+use crate::{RunMode, hal::ccm};
 
 /// Specify the PLL1 DIV_SEL for a given run mode.
 const fn div_sel(run_mode: RunMode) -> u32 {
diff --git a/board/src/imxrt10xx/clock_tree/pll6_ahb.rs b/board/src/imxrt10xx/clock_tree/pll6_ahb.rs
@@ -6,7 +6,7 @@
 //! - if an ARM divider exists, it's set to 1.
 //! - if a PERIPH_CLK2 divider exists, it's set to 1.
 
-use crate::{hal::ccm, ral, RunMode};
+use crate::{RunMode, hal::ccm, ral};
 
 /// Specify the AHB divider for a given run mode.
 const fn ahb_divider(run_mode: RunMode) -> u32 {
diff --git a/board/src/imxrt10xx/power.rs b/board/src/imxrt10xx/power.rs
@@ -1,4 +1,4 @@
-use crate::{hal::dcdc, ral, RunMode};
+use crate::{RunMode, hal::dcdc, ral};
 
 /// Set the target power for the provided `run_mode`.
 pub fn set_target_power(dcdc: &mut ral::dcdc::DCDC, run_mode: RunMode) {
diff --git a/board/src/imxrt1170evk-cm7.rs b/board/src/imxrt1170evk-cm7.rs
@@ -1,6 +1,6 @@
 //! i.MX RT 1170 EVK board configuration, supporting CM7 applications.
 
-use crate::{hal, iomuxc::imxrt1170 as iomuxc, ral, GPT1_DIVIDER, GPT2_DIVIDER, RUN_MODE};
+use crate::{GPT1_DIVIDER, GPT2_DIVIDER, RUN_MODE, hal, iomuxc::imxrt1170 as iomuxc, ral};
 
 mod imxrt11xx {
     pub(super) mod clock_tree;
@@ -39,7 +39,7 @@ const CLOCK_GATES: &[clock_gate::Locator] = &[
 ];
 
 pub(crate) unsafe fn configure() {
-    let mut ccm = ral::ccm::CCM::instance();
+    let mut ccm = unsafe { ral::ccm::CCM::instance() };
 
     prepare_clock_tree(&mut ccm);
     CLOCK_GATES
diff --git a/board/src/imxrt11xx/clock_tree.rs b/board/src/imxrt11xx/clock_tree.rs
@@ -13,9 +13,9 @@
 //! See the 10xx documentation for an example.
 
 use crate::{
+    RunMode,
     hal::ccm::XTAL_OSCILLATOR_HZ,
     ral::{self, ccm::CCM},
-    RunMode,
 };
 
 /// A clock source.
diff --git a/board/src/lib.rs b/board/src/lib.rs
@@ -248,7 +248,7 @@ type Pit = crate::ral::pit::PIT1;
 #[allow(unused)]
 mod board_interrupts {
     pub type Vector = unsafe extern "C" fn();
-    extern "C" {
+    unsafe extern "C" {
         pub fn BOARD_CONSOLE();
         pub fn BOARD_BUTTON();
         pub fn BOARD_SPI();
diff --git a/board/src/ral_shim.rs b/board/src/ral_shim.rs
@@ -31,7 +31,7 @@ pub const BOARD_DMA_B_INDEX: usize = 11;
 /// Only safe when called from the imxrt-hal examples support crate.
 /// It might not even be safe there!
 pub(crate) unsafe fn shim_vectors() {
-    extern "C" {
+    unsafe extern "C" {
         // Defined in cortex-m-rt crate. Definitely not marked
         // 'mut', nor does it use UnsafeCell. YOLO.
         // (No one observes the __INTERRUPTS immutable static anyway.)
@@ -42,7 +42,7 @@ pub(crate) unsafe fn shim_vectors() {
 
     cortex_m::interrupt::free(|_| {
         for (nr, isr) in INTERRUPTS {
-            __INTERRUPTS[*nr as usize].get().write_volatile(*isr);
+            unsafe { __INTERRUPTS[*nr as usize].get().write_volatile(*isr) };
         }
 
         cortex_m::asm::dsb();
diff --git a/board/src/teensy4.rs b/board/src/teensy4.rs
@@ -268,9 +268,9 @@ pub(crate) const CLOCK_GATES: &[clock_gate::Locator] = &[
 /// set alternates here.
 fn configure_pins(
     super::Pads {
-        ref mut gpio_ad_b0,
-        ref mut gpio_ad_b1,
-        ref mut gpio_b0,
+        gpio_ad_b0,
+        gpio_ad_b1,
+        gpio_b0,
         ..
     }: &mut super::Pads,
 ) {
diff --git a/board/src/vmu-rt1170-cm7.rs b/board/src/vmu-rt1170-cm7.rs
@@ -1,6 +1,6 @@
 //! VMU RT1170 board configuration, supporting CM7 applications.
 
-use crate::{hal, iomuxc::imxrt1170 as iomuxc, ral, GPT1_DIVIDER, GPT2_DIVIDER, RUN_MODE};
+use crate::{GPT1_DIVIDER, GPT2_DIVIDER, RUN_MODE, hal, iomuxc::imxrt1170 as iomuxc, ral};
 
 mod imxrt11xx {
     pub(super) mod clock_tree;
@@ -39,7 +39,7 @@ const CLOCK_GATES: &[clock_gate::Locator] = &[
 ];
 
 pub(crate) unsafe fn configure() {
-    let mut ccm = ral::ccm::CCM::instance();
+    let mut ccm = unsafe { ral::ccm::CCM::instance() };
 
     prepare_clock_tree(&mut ccm);
     CLOCK_GATES
diff --git a/examples/rtic_sai_pcm5102.rs b/examples/rtic_sai_pcm5102.rs
@@ -55,11 +55,7 @@ fn sine(t: u32) -> u16 {
 
 /// Generate a square wave sample
 fn square(t: u32) -> u16 {
-    if (t % 128) > 64 {
-        32767
-    } else {
-        0
-    }
+    if (t % 128) > 64 { 32767 } else { 0 }
 }
 
 #[rtic::app(device = board, peripherals = false, dispatchers = [BOARD_SWTASK0])]
diff --git a/examples/rtic_sai_wm8960.rs b/examples/rtic_sai_wm8960.rs
@@ -45,11 +45,7 @@ fn sine(t: u32) -> u16 {
 
 /// Generate a square wave sample
 fn square(t: u32) -> u16 {
-    if (t % 128) > 64 {
-        32767
-    } else {
-        0
-    }
+    if (t % 128) > 64 { 32767 } else { 0 }
 }
 
 #[rtic::app(device = board, peripherals = false, dispatchers = [BOARD_SWTASK0])]
diff --git a/logging/CHANGELOG.md b/logging/CHANGELOG.md
@@ -10,6 +10,8 @@
 - `usb-device` 0.3
 - `usbd-serial` 0.2
 
+**BREAKING** Upgrade to Rust 2024.
+
 ## [0.1.2] 2024-06-06
 
 Increase the USB bulk max packet size (MPS) from 64 to 512. This is required
diff --git a/logging/src/log.rs b/logging/src/log.rs
@@ -16,7 +16,7 @@ mod frontend;
 pub use filters::Filter;
 use filters::Filters;
 
-use crate::{Poller, BUFFER};
+use crate::{BUFFER, Poller};
 
 #[cfg(feature = "lpuart")]
 use imxrt_hal::{dma::channel::Channel, lpuart::Lpuart};
diff --git a/logging/src/usbd.rs b/logging/src/usbd.rs
@@ -98,24 +98,22 @@ impl Backend {
         self.class.read_packet(&mut []).ok();
 
         // There's no need to wait if we were are newly configured.
-        if check_consumer {
-            if let Ok(grant) = self.consumer.read() {
-                let buf = grant.buf();
-                // Don't try to write more than we can fit in a single packet!
-                // See the usbd-serial documentation for this caveat. We didn't
-                // statically allocate enough space for anything larger.
-                if let Ok(written) = self
-                    .class
-                    .write_packet(&buf[..MAX_PACKET_SIZE.min(buf.len())])
-                {
-                    grant.release(written);
-                    // Log data is in the intermediate buffer, so it's OK to release the grant.
-                    //
-                    // If the I/O fails here, we'll try again on the next poll. There's no guarantee
-                    // we'll see a improvement though...
-                }
-            } // else, no data, or some error. Let those logs accumulate!
-        }
+        if check_consumer && let Ok(grant) = self.consumer.read() {
+            let buf = grant.buf();
+            // Don't try to write more than we can fit in a single packet!
+            // See the usbd-serial documentation for this caveat. We didn't
+            // statically allocate enough space for anything larger.
+            if let Ok(written) = self
+                .class
+                .write_packet(&buf[..MAX_PACKET_SIZE.min(buf.len())])
+            {
+                grant.release(written);
+                // Log data is in the intermediate buffer, so it's OK to release the grant.
+                //
+                // If the I/O fails here, we'll try again on the next poll. There's no guarantee
+                // we'll see a improvement though...
+            }
+        } // else, no data, or some error. Let those logs accumulate!
     }
 }
 
diff --git a/src/chip/drivers/adc.rs b/src/chip/drivers/adc.rs
@@ -28,7 +28,7 @@
 //! # Some(()) }();
 //! ```
 
-use crate::iomuxc::adc::{prepare, Pin};
+use crate::iomuxc::adc::{Pin, prepare};
 use crate::ral;
 
 /// Any ADC instance.
diff --git a/src/common/lpi2c.rs b/src/common/lpi2c.rs
@@ -199,11 +199,7 @@ impl Lpi2c {
     #[inline]
     pub fn read_data_register(&self) -> Option<u8> {
         let (empty, data) = ral::read_reg!(ral::lpi2c, self.lpi2c, MRDR, RXEMPTY, DATA);
-        if empty != 0 {
-            None
-        } else {
-            Some(data as u8)
-        }
+        if empty != 0 { None } else { Some(data as u8) }
     }
 
     /// Temporarily disable the LPI2C peripheral.
@@ -598,7 +594,7 @@ impl ControllerCommand {
     /// Turn a command into its raw representation, permitting
     /// 32-bit writes to the transmit data register.
     const fn raw(self) -> u32 {
-        use crate::ral::lpi2c::MTDR::CMD::{offset as OFFSET, RW::*};
+        use crate::ral::lpi2c::MTDR::CMD::{RW::*, offset as OFFSET};
         match self {
             Self::Transmit { byte } => (CMD_0 << OFFSET) | byte as u32,
             Self::Receive { count } => (CMD_1 << OFFSET) | count.saturating_sub(1) as u32,
@@ -1019,11 +1015,7 @@ const fn line_latency_cycles(filter: u8, risetime: u8, prescaler: Prescaler) ->
 const fn compute_clk(hz: u32, baud: ClockSpeed, prescaler: Prescaler, scl_latency: u8) -> u8 {
     let clk: u32 =
         (hz / prescaler.divider() as u32 / baud.frequency() - scl_latency as u32 - 2) / 3;
-    if clk > 0xFF {
-        0xFFu8
-    } else {
-        clk as u8
-    }
+    if clk > 0xFF { 0xFFu8 } else { clk as u8 }
 }
 
 impl Timing {
@@ -1132,11 +1124,7 @@ impl Timing {
     /// Define LPI2C timings by the clock configuration values, and a prescaler.
     pub const fn new(clock_configuration: ClockConfiguration, prescaler: Prescaler) -> Self {
         const fn max(left: u32, right: u32) -> u32 {
-            if left > right {
-                left
-            } else {
-                right
-            }
+            if left > right { left } else { right }
         }
         let busidle = max(
             (clock_configuration.clklo as u32 + clock_configuration.sethold as u32 + 2) * 2,
diff --git a/src/common/lpspi.rs b/src/common/lpspi.rs
@@ -88,7 +88,7 @@ use crate::ral;
 /// Any LPSPI instance.
 type AnyInstance = crate::AnyInstance<ral::lpspi::RegisterBlock>;
 
-pub use eh02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
+pub use eh02::spi::{MODE_0, MODE_1, MODE_2, MODE_3, Mode, Phase, Polarity};
 
 /// Data direction.
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
diff --git a/src/common/lpuart.rs b/src/common/lpuart.rs
@@ -553,18 +553,10 @@ impl Baud {
     /// is the intended baud rate.
     pub const fn compute(source_clock_hz: u32, baud: u32) -> Baud {
         const fn max(left: u32, right: u32) -> u32 {
-            if left > right {
-                left
-            } else {
-                right
-            }
+            if left > right { left } else { right }
         }
         const fn min(left: u32, right: u32) -> u32 {
-            if left < right {
-                left
-            } else {
-                right
-            }
+            if left < right { left } else { right }
         }
 
         let mut err = u32::MAX;
@@ -1112,8 +1104,10 @@ mod tests {
         assert_eq!(Status::stat_mask().stat_bits(), 0x01FF_0000);
         assert_eq!(Status::W1C.bits(), 0x001F_3000);
 
-        assert!(Status::from_registers(0, (1 << 17) | (1 << 16))
-            .contains(Status::TRANSMIT_OVERFLOW | Status::RECEIVE_UNDERFLOW));
+        assert!(
+            Status::from_registers(0, (1 << 17) | (1 << 16))
+                .contains(Status::TRANSMIT_OVERFLOW | Status::RECEIVE_UNDERFLOW)
+        );
         assert!(Status::from_registers(u32::MAX, 0).contains(Status::stat_mask()));
 
         assert!(Status::all().contains(Status::TRANSMIT_EMPTY));

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-use crate::{hal::dcdc, ral, RunMode};`
	`1`	`+use crate::{RunMode, hal::dcdc, ral};`
`2`	`2`
`3`	`3`	/// Set the target power for the provided `run_mode`.
`4`	`4`	`pub fn set_target_power(dcdc: &mut ral::dcdc::DCDC, run_mode: RunMode) {`