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mickflemmlinvjw
mickflemm
authored and
linvjw
committed
ath5k: Use usleep_range where possible
Use usleep_range where possible to reduce busy waits Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
1 parent ce169ac commit 1846ac3

4 files changed

Lines changed: 20 additions & 20 deletions

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‎drivers/net/wireless/ath/ath5k/attach.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,7 @@ int ath5k_hw_init(struct ath5k_hw *ah)
298298

299299
/* Reset SERDES to load new settings */
300300
ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
301-
mdelay(1);
301+
usleep_range(1000, 1500);
302302
}
303303

304304
/* Get misc capabilities */

‎drivers/net/wireless/ath/ath5k/pci.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
9898
0xffff);
9999
return true;
100100
}
101-
udelay(15);
101+
usleep_range(15, 20);
102102
}
103103

104104
return false;

‎drivers/net/wireless/ath/ath5k/phy.c‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band)
5858
return 0;
5959
}
6060

61-
mdelay(2);
61+
usleep_range(2000, 2500);
6262

6363
/* ...wait until PHY is ready and read the selected radio revision */
6464
ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
@@ -308,9 +308,9 @@ static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
308308
delay = delay << 2;
309309
/* XXX: /2 on turbo ? Let's be safe
310310
* for now */
311-
udelay(100 + delay);
311+
usleep_range(100 + delay, 100 + (2 * delay));
312312
} else {
313-
mdelay(1);
313+
usleep_range(1000, 1500);
314314
}
315315
}
316316

@@ -1083,7 +1083,7 @@ static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
10831083
data = ath5k_hw_rf5110_chan2athchan(channel);
10841084
ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
10851085
ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1086-
mdelay(1);
1086+
usleep_range(1000, 1500);
10871087

10881088
return 0;
10891089
}
@@ -1454,7 +1454,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
14541454
beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
14551455
ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
14561456

1457-
mdelay(2);
1457+
usleep_range(2000, 2500);
14581458

14591459
/*
14601460
* Set the channel (with AGC turned off)
@@ -1467,7 +1467,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
14671467
* Activate PHY and wait
14681468
*/
14691469
ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1470-
mdelay(1);
1470+
usleep_range(1000, 1500);
14711471

14721472
AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
14731473

@@ -1504,7 +1504,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
15041504
ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
15051505
AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
15061506

1507-
mdelay(1);
1507+
usleep_range(1000, 1500);
15081508

15091509
/*
15101510
* Enable calibration and wait until completion
@@ -3397,7 +3397,7 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
33973397
if (ret)
33983398
return ret;
33993399

3400-
mdelay(1);
3400+
usleep_range(1000, 1500);
34013401

34023402
/*
34033403
* Write RF buffer
@@ -3418,10 +3418,10 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
34183418
}
34193419

34203420
} else if (ah->ah_version == AR5K_AR5210) {
3421-
mdelay(1);
3421+
usleep_range(1000, 1500);
34223422
/* Disable phy and wait */
34233423
ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
3424-
mdelay(1);
3424+
usleep_range(1000, 1500);
34253425
}
34263426

34273427
/* Set channel on PHY */
@@ -3447,7 +3447,7 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
34473447
for (i = 0; i <= 20; i++) {
34483448
if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
34493449
break;
3450-
udelay(200);
3450+
usleep_range(200, 250);
34513451
}
34523452
ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
34533453

‎drivers/net/wireless/ath/ath5k/reset.c‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -357,7 +357,7 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
357357
ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
358358

359359
/* Wait at least 128 PCI clocks */
360-
udelay(15);
360+
usleep_range(15, 20);
361361

362362
if (ah->ah_version == AR5K_AR5210) {
363363
val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
@@ -422,7 +422,7 @@ static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
422422
regval = __raw_readl(reg);
423423
__raw_writel(regval | val, reg);
424424
regval = __raw_readl(reg);
425-
udelay(100);
425+
usleep_range(100, 150);
426426

427427
/* Bring BB/MAC out of reset */
428428
__raw_writel(regval & ~val, reg);
@@ -493,7 +493,7 @@ static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
493493

494494
ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
495495
AR5K_SLEEP_CTL);
496-
udelay(15);
496+
usleep_range(15, 20);
497497

498498
for (i = 200; i > 0; i--) {
499499
/* Check if the chip did wake up */
@@ -502,7 +502,7 @@ static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
502502
break;
503503

504504
/* Wait a bit and retry */
505-
udelay(50);
505+
usleep_range(50, 75);
506506
ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
507507
AR5K_SLEEP_CTL);
508508
}
@@ -563,7 +563,7 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
563563
ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
564564
AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
565565
AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
566-
mdelay(2);
566+
usleep_range(2000, 2500);
567567
} else {
568568
ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
569569
AR5K_RESET_CTL_BASEBAND | bus_flags);
@@ -621,7 +621,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
621621
ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
622622
AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
623623
AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
624-
mdelay(2);
624+
usleep_range(2000, 2500);
625625
} else {
626626
if (ath5k_get_bus_type(ah) == ATH_AHB)
627627
ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
@@ -739,7 +739,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
739739
/* ...update PLL if needed */
740740
if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
741741
ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
742-
udelay(300);
742+
usleep_range(300, 350);
743743
}
744744

745745
/* ...set the PHY operating mode */

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