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| 1 | +#![no_std] |
| 2 | +#![no_main] |
| 3 | + |
| 4 | +#[allow(unused_imports)] |
| 5 | +use embedded_hal::blocking::i2c::{Read, Write}; |
| 6 | +use embedded_hal::digital::v2::InputPin; |
| 7 | +use { |
| 8 | + core::{ |
| 9 | + panic::PanicInfo, |
| 10 | + sync::atomic::{compiler_fence, Ordering}, |
| 11 | + }, |
| 12 | + hal::{ |
| 13 | + gpio::{p0::Parts, Input, Pin, PullUp}, |
| 14 | + gpiote::Gpiote, |
| 15 | + pac::TWIM0, |
| 16 | + twim::*, |
| 17 | + }, |
| 18 | + nrf52840_hal as hal, |
| 19 | + rtic::cyccnt::U32Ext, |
| 20 | + rtt_target::{rprintln, rtt_init_print}, |
| 21 | +}; |
| 22 | + |
| 23 | +#[rtic::app(device = crate::hal::pac, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] |
| 24 | +const APP: () = { |
| 25 | + struct Resources { |
| 26 | + twim: Twim<TWIM0>, |
| 27 | + gpiote: Gpiote, |
| 28 | + btn1: Pin<Input<PullUp>>, |
| 29 | + btn2: Pin<Input<PullUp>>, |
| 30 | + btn3: Pin<Input<PullUp>>, |
| 31 | + btn4: Pin<Input<PullUp>>, |
| 32 | + } |
| 33 | + |
| 34 | + #[init] |
| 35 | + fn init(mut ctx: init::Context) -> init::LateResources { |
| 36 | + let _clocks = hal::clocks::Clocks::new(ctx.device.CLOCK).enable_ext_hfosc(); |
| 37 | + ctx.core.DCB.enable_trace(); |
| 38 | + ctx.core.DWT.enable_cycle_counter(); |
| 39 | + rtt_init_print!(); |
| 40 | + |
| 41 | + let p0 = Parts::new(ctx.device.P0); |
| 42 | + let scl = p0.p0_30.into_floating_input().degrade(); |
| 43 | + let sda = p0.p0_31.into_floating_input().degrade(); |
| 44 | + let btn1 = p0.p0_11.into_pullup_input().degrade(); |
| 45 | + let btn2 = p0.p0_12.into_pullup_input().degrade(); |
| 46 | + let btn3 = p0.p0_24.into_pullup_input().degrade(); |
| 47 | + let btn4 = p0.p0_25.into_pullup_input().degrade(); |
| 48 | + |
| 49 | + let gpiote = Gpiote::new(ctx.device.GPIOTE); |
| 50 | + gpiote.port().input_pin(&btn1).low(); |
| 51 | + gpiote.port().input_pin(&btn2).low(); |
| 52 | + gpiote.port().input_pin(&btn3).low(); |
| 53 | + gpiote.port().input_pin(&btn4).low(); |
| 54 | + gpiote.port().enable_interrupt(); |
| 55 | + |
| 56 | + let twim = Twim::new(ctx.device.TWIM0, Pins { scl, sda }, Frequency::K100); |
| 57 | + |
| 58 | + init::LateResources { |
| 59 | + twim, |
| 60 | + gpiote, |
| 61 | + btn1, |
| 62 | + btn2, |
| 63 | + btn3, |
| 64 | + btn4, |
| 65 | + } |
| 66 | + } |
| 67 | + |
| 68 | + #[idle] |
| 69 | + fn idle(_: idle::Context) -> ! { |
| 70 | + rprintln!("Press button 1 to READ from addr 0x1A"); |
| 71 | + rprintln!("Press button 2 to WRITE to addr 0x1A"); |
| 72 | + rprintln!("Press button 3 to READ from addr 0x1B"); |
| 73 | + rprintln!("Press button 4 to WRITE from addr 0x1B"); |
| 74 | + loop { |
| 75 | + cortex_m::asm::wfi(); |
| 76 | + } |
| 77 | + } |
| 78 | + |
| 79 | + #[task(binds = GPIOTE, resources = [gpiote], schedule = [debounce])] |
| 80 | + fn on_gpiote(ctx: on_gpiote::Context) { |
| 81 | + ctx.resources.gpiote.reset_events(); |
| 82 | + ctx.schedule.debounce(ctx.start + 3_000_000.cycles()).ok(); |
| 83 | + } |
| 84 | + |
| 85 | + #[task(resources = [twim, gpiote, btn1, btn2, btn3, btn4])] |
| 86 | + fn debounce(ctx: debounce::Context) { |
| 87 | + let twim = ctx.resources.twim; |
| 88 | + if ctx.resources.btn1.is_low().unwrap() { |
| 89 | + rprintln!("\nREAD from address 0x1A"); |
| 90 | + let rx_buf = &mut [0; 8][..]; |
| 91 | + let res = twim.read(0x1A, rx_buf); |
| 92 | + rprintln!("Result: {:?}\n{:?}", res, rx_buf); |
| 93 | + } |
| 94 | + if ctx.resources.btn2.is_low().unwrap() { |
| 95 | + rprintln!("\nWRITE to address 0x1A"); |
| 96 | + let tx_buf = [1, 2, 3, 4, 5, 6, 7, 8]; |
| 97 | + let res = twim.write(0x1A, &tx_buf[..]); |
| 98 | + rprintln!("Result: {:?}\n{:?}", res, tx_buf); |
| 99 | + } |
| 100 | + if ctx.resources.btn3.is_low().unwrap() { |
| 101 | + rprintln!("\nREAD from address 0x1B"); |
| 102 | + let rx_buf = &mut [0; 4][..]; |
| 103 | + let res = twim.read(0x1B, rx_buf); |
| 104 | + rprintln!("Result: {:?}\n{:?}", res, rx_buf); |
| 105 | + } |
| 106 | + if ctx.resources.btn4.is_low().unwrap() { |
| 107 | + rprintln!("\nWRITE to address 0x1B"); |
| 108 | + let tx_buf = [9, 10, 11, 12]; |
| 109 | + let res = twim.write(0x1B, &tx_buf[..]); |
| 110 | + rprintln!("Result: {:?}\n{:?}", res, tx_buf); |
| 111 | + } |
| 112 | + } |
| 113 | + |
| 114 | + extern "C" { |
| 115 | + fn SWI0_EGU0(); |
| 116 | + } |
| 117 | +}; |
| 118 | + |
| 119 | +#[inline(never)] |
| 120 | +#[panic_handler] |
| 121 | +fn panic(info: &PanicInfo) -> ! { |
| 122 | + cortex_m::interrupt::disable(); |
| 123 | + rprintln!("{}", info); |
| 124 | + loop { |
| 125 | + compiler_fence(Ordering::SeqCst); |
| 126 | + } |
| 127 | +} |
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