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Merge pull request #159 from bugadani/bugfix/uneven
Fix incorrect logic in transfer_split_uneven
2 parents 9a5265f + 82bdf81 commit ba216e5

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nrf-hal-common/src/spim.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -340,7 +340,7 @@ where
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// Don't return early, as we must reset the CS pin
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let res = txi
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.zip(rxi)
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.take_while(|(t, r)| t.is_some() && r.is_some())
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.take_while(|(t, r)| t.is_some() || r.is_some())
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// We also turn the slices into either a DmaSlice (if there was data), or a null
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// DmaSlice (if there is no data)
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.map(|(t, r)| {

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