ch06

Isle Chapter 6 - Input Output

These Verilog designs accompany Input Output, chapter 6 of Building Isle. See also: Chapter 6 Software.

See boards for build and programming instructions. See Serial to Isle for advice on connecting to Isle UART via USB.

Verilog Modules

The chapter 6 design uses the following Verilog modules:

• book/ch06/ch06.v
• cpu/FemtoRV32.v
• devs/gfx_dev.v
• devs/sys_dev.v
• devs/uart_dev.v
• gfx/display.v
• gfx/font_glyph.v
• gfx/textmode.v
• gfx/tmds_encoder.v (not used by Verilator sim)
• io/uart_rx.v
• math/lfsr.v
• mem/clut.v
• mem/fifo_sync.v
• mem/rom_sync.v
• mem/sysram.v
• mem/tram.v
• sys/xd.v

Each board has its own top module plus relevant architecture-specific modules under arch/ecp5 and arch/xc7; check board make/build files for details.