Essential Verilog designs from Project F that don't fit in another category. You can freely build on these MIT licensed designs. Get an overview of the whole lib from the Verilog Library blog.
- debounce.sv - button debouncing
- xc7/async_reset.sv - asynchronous reset for Xilinx 7 Series
Locate Vivado test benches in the xc7 directory.
Find other modules in the Library.
Button debouncing is used in Hello Arty Part 3 and Pong.
These modules use a little SystemVerilog to make Verilog more pleasant, see the main Library README for details.