A UART was one of the first SystemVerilog designs I created. These designs are not polished, but I hope you find them useful. You can freely build on these MIT licensed designs. Get an overview of the whole lib from the Verilog Library blog.
- uart_baud.sv - UART baud rate generator
- uart_rx.sv - UART receiver (to FPGA)
- uart_tx.sv - UART transmitter (from FPGA)
Test benches still need to be added for UART.
- top_uart.sv - echo example at 9600 baud (8N1)
NB. Transmit and receive are from the point of view of the FPGA.
No Project F blog posts reference these modules as yet.
These modules use a little SystemVerilog to make Verilog more pleasant, see the main Library README for details.