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Add generic_timer tests for Armv7-A
Requires we change the emulated CPU from Cortex-A8 to Cortex-A15, as Cortex-A8 doesn't have the timer extensions. That in turn meant we booted into EL2, so we needed to bounce ourselves into EL1 that the examples were expecting. And that meant making a bunch of Hyp registers available on Armv7-A and Armv8-R, and changing the Armv7-A start-up routine to be the Armv8-R routine.
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.cargo/config.toml

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@@ -23,16 +23,16 @@ runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nogr
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runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel"
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[target.armv7a-none-eabihf]
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runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
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runner = "qemu-system-arm -machine versatileab -cpu cortex-a15 -semihosting -nographic -audio none -kernel"
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[target.thumbv7a-none-eabihf]
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runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
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runner = "qemu-system-arm -machine versatileab -cpu cortex-a15 -semihosting -nographic -audio none -kernel"
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[target.armv7a-none-eabi]
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runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
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runner = "qemu-system-arm -machine versatileab -cpu cortex-a15 -semihosting -nographic -audio none -kernel"
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[target.thumbv7a-none-eabi]
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runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
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runner = "qemu-system-arm -machine versatileab -cpu cortex-a15 -semihosting -nographic -audio none -kernel"
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[target.armv6-none-eabihf]
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runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"

aarch32-cpu/src/cache.rs

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//! Helper functions for cache operations
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use arbitrary_int::u3;
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use crate::register::{Dccimvac, Dccisw, Dccmvac, Dccsw, Dcimvac, Dcisw, SysRegWrite};

aarch32-cpu/src/generic_timer/el0.rs

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use crate::register;
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/// Represents our Generic Timer when we are running at EL0.
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/// Represents our Physical Timer when we are running at EL0.
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///
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/// Note that for most of these APIs to work, EL0 needs to have been granted
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/// access using methods like
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}
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}
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/// Represents our Virtual Timer when we are running at EL0.
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///
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/// Note that for most of these APIs to work, EL0 needs to have been granted
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/// access using methods like
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/// [El1PhysicalTimer::el0_access_virtual_counter](crate::generic_timer::El1VirtualTimer::el0_access_virtual_counter).
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pub struct El0VirtualTimer();
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impl El0VirtualTimer {

aarch32-cpu/src/mmu.rs

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//! Code and types for use with MMU programming on a VMSA (Virtual Memory System Architecture) platform
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//! Support for the VMSAv7 MMU
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use arbitrary_int::{u12, u2, u3, u4};
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aarch32-cpu/src/register/armv8r/mod.rs

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//! Access registers for Armv8-R only
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pub mod hacr;
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pub mod hactlr;
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pub mod hactlr2;
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pub mod hadfsr;
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pub mod haifsr;
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pub mod hamair0;
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pub mod hamair1;
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pub mod hcptr;
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pub mod hcr;
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pub mod hcr2;
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pub mod hdcr;
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pub mod hdfar;
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pub mod hifar;
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pub mod hmair0;
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pub mod hmair1;
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pub mod hmpuir;
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pub mod hpfar;
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pub mod hprbar;
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pub mod hprbar0;
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pub mod hprbar1;
@@ -53,11 +37,6 @@ pub mod hprlar7;
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pub mod hprlar8;
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pub mod hprlar9;
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pub mod hprselr;
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pub mod hsctlr;
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pub mod hsr;
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pub mod hstr;
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pub mod htpidr;
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pub mod hvbar;
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pub mod prbar;
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pub mod prbar0;
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pub mod prbar1;
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pub mod prselr;
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pub mod vbar;
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pub use hacr::Hacr;
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pub use hactlr::Hactlr;
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pub use hactlr2::Hactlr2;
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pub use hadfsr::Hadfsr;
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pub use haifsr::Haifsr;
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pub use hamair0::Hamair0;
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pub use hamair1::Hamair1;
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pub use hcptr::Hcptr;
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pub use hcr::Hcr;
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pub use hcr2::Hcr2;
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pub use hdcr::Hdcr;
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pub use hdfar::Hdfar;
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pub use hifar::Hifar;
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pub use hmair0::Hmair0;
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pub use hmair1::Hmair1;
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pub use hmpuir::Hmpuir;
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pub use hpfar::Hpfar;
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pub use hprbar::Hprbar;
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pub use hprbar0::Hprbar0;
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pub use hprbar1::Hprbar1;
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pub use hprlar8::Hprlar8;
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pub use hprlar9::Hprlar9;
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pub use hprselr::Hprselr;
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pub use hsctlr::Hsctlr;
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pub use hsr::Hsr;
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pub use hstr::Hstr;
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pub use htpidr::Htpidr;
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pub use hvbar::Hvbar;
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pub use prbar::Prbar;
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pub use prbar0::Prbar0;
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pub use prbar1::Prbar1;
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