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Add Tomasulo correctness test and IPC performance benchmark apps
 Two new sw/apps for validating and measuring Tomasulo out-of-order execution: tomasulo_test (10 tests covering RAW/WAR/WAW hazards, OOO execution, latency bypass, RS saturation, memory disambiguation, complex dependency chains, branches, and CDB contention) and tomasulo_perf (7 IPC benchmarks comparing dependent vs independent instruction chains using hardware cycle/instret counters). Both use C with inline asm volatile blocks to emit exact hazard-creating instruction sequences, and integrate into the existing cocotb test_real_program framework via TEST_REGISTRY entries.
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‎sw/apps/tomasulo_perf/Makefile‎

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# Copyright 2026 Two Sigma Open Source, LLC
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# Makefile for Tomasulo Performance Measurement
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# Measures IPC across workloads to quantify OOO execution benefit
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SRC_C := ../../lib/src/uart.c tomasulo_perf.c
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include ../../common/common.mk

‎sw/apps/tomasulo_perf/tomasulo_perf.c‎

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/*
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* Copyright 2026 Two Sigma Open Source, LLC
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* Tomasulo Performance Measurement
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*
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* Measures Instructions Per Cycle (IPC) across different workloads to
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* quantify the benefit of out-of-order execution via Tomasulo's algorithm.
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*
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* Key comparison: dependent vs independent instruction chains.
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* - Dependent chains serialize on data hazards (IPC limited to ~1.0)
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* - Independent chains can exploit ILP (IPC scales with issue width)
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* - The ratio between them shows the OOO execution benefit
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*
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* Uses hardware cycle and instret counters (Zicntr CSRs) for measurement.
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* IPC is reported as IPC*100 (integer, so 150 means IPC = 1.50).
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*
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* Benchmarks:
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* 1. Dependent ADD chain (worst-case ILP: serialized)
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* 2. Independent ADD chains (best-case ILP: fully parallel)
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* 3. Dependent MUL chain (long-latency serialized)
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* 4. Independent MUL chains (long-latency parallel)
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* 5. Mixed MUL + ADD (latency hiding)
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* 6. Load-store throughput (memory subsystem)
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* 7. Branch-heavy loop (branch prediction + OOO)
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*/
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#include "csr.h"
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#include "uart.h"
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#include <stdint.h>
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static void print_result(uint32_t cycles, uint32_t instrs)
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{
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uint32_t ipc_x100 = cycles ? (instrs * 100) / cycles : 0;
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uart_printf(" Cycles: %lu Instrs: %lu IPC*100: %lu\n",
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(unsigned long) cycles,
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(unsigned long) instrs,
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(unsigned long) ipc_x100);
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}
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int main(void)
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{
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uint32_t c0, c1, i0, i1;
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uart_printf("\n");
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uart_printf("============================================================\n");
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uart_printf(" TOMASULO PERFORMANCE MEASUREMENT\n");
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uart_printf("============================================================\n");
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uart_printf(" IPC*100: 100 = 1.0 IPC, 150 = 1.5 IPC, etc.\n\n");
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/* ===================================================================== */
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/* Benchmark 1: Dependent ADD chain (100 instructions) */
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/* Each ADD reads the result of the previous one - no ILP possible. */
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/* Baseline for comparison: OOO cannot help here. */
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/* ===================================================================== */
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uart_printf("Bench 1: Dependent ADD chain (100 instrs)\n");
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c0 = rdcycle();
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i0 = rdinstret();
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__asm__ volatile("addi t0, zero, 1\n"
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".rept 100\n"
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"add t0, t0, t0\n"
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".endr\n"
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:
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:
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: "t0");
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c1 = rdcycle();
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i1 = rdinstret();
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print_result(c1 - c0, i1 - i0);
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/* ===================================================================== */
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/* Benchmark 2: Independent ADD chains (4 x 25 = 100 instructions) */
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/* 4 chains with no cross-dependencies - ideal for OOO execution. */
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/* IPC should be higher than Bench 1 if OOO is working. */
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/* ===================================================================== */
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uart_printf("Bench 2: Independent ADD chains (4x25 = 100 instrs)\n");
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c0 = rdcycle();
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i0 = rdinstret();
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__asm__ volatile("addi t0, zero, 1\n"
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"addi t1, zero, 2\n"
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"addi t2, zero, 3\n"
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"addi t3, zero, 4\n"
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".rept 25\n"
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"add t0, t0, t0\n"
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"add t1, t1, t1\n"
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"add t2, t2, t2\n"
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"add t3, t3, t3\n"
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".endr\n"
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:
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:
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: "t0", "t1", "t2", "t3");
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c1 = rdcycle();
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i1 = rdinstret();
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print_result(c1 - c0, i1 - i0);
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/* ===================================================================== */
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/* Benchmark 3: Dependent MUL chain (50 instructions) */
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/* MUL has multi-cycle latency, so a dependent chain is very slow. */
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/* Multiply by 1 to keep the value stable (avoids overflow). */
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/* ===================================================================== */
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uart_printf("Bench 3: Dependent MUL chain (50 instrs)\n");
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c0 = rdcycle();
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i0 = rdinstret();
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__asm__ volatile("addi t0, zero, 3\n"
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"addi t1, zero, 1\n"
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".rept 50\n"
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"mul t0, t0, t1\n"
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".endr\n"
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:
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:
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: "t0", "t1");
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c1 = rdcycle();
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i1 = rdinstret();
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print_result(c1 - c0, i1 - i0);
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/* ===================================================================== */
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/* Benchmark 4: Independent MUL chains (4 x 12 = 48 instructions) */
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/* 4 independent MUL chains. If the MUL unit is pipelined or there are */
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/* multiple MUL reservation stations, these can overlap. */
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/* ===================================================================== */
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uart_printf("Bench 4: Independent MUL chains (4x12 = 48 instrs)\n");
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c0 = rdcycle();
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i0 = rdinstret();
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__asm__ volatile("addi t0, zero, 2\n"
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"addi t1, zero, 3\n"
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"addi t2, zero, 5\n"
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"addi t3, zero, 7\n"
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"addi t4, zero, 1\n"
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".rept 12\n"
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"mul t0, t0, t4\n"
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"mul t1, t1, t4\n"
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"mul t2, t2, t4\n"
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"mul t3, t3, t4\n"
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".endr\n"
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:
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:
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: "t0", "t1", "t2", "t3", "t4");
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c1 = rdcycle();
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i1 = rdinstret();
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print_result(c1 - c0, i1 - i0);
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/* ===================================================================== */
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/* Benchmark 5: Mixed MUL + independent ADD (100 instruction pairs) */
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/* Tests whether short-latency ADDs can execute while MUL is in flight. */
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/* An OOO machine should overlap the ADD with the MUL stall. */
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/* ===================================================================== */
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uart_printf("Bench 5: Mixed MUL+ADD (50 pairs = 100 instrs)\n");
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c0 = rdcycle();
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i0 = rdinstret();
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__asm__ volatile("addi t0, zero, 1\n"
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"addi t1, zero, 1\n"
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"addi t2, zero, 0\n"
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"addi t3, zero, 1\n"
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".rept 50\n"
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"mul t0, t0, t1\n" /* Long latency (dependent chain) */
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"add t2, t2, t3\n" /* Short latency (independent of MUL) */
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".endr\n"
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:
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:
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: "t0", "t1", "t2", "t3");
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c1 = rdcycle();
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i1 = rdinstret();
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print_result(c1 - c0, i1 - i0);
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/* ===================================================================== */
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/* Benchmark 6: Load-store throughput (50 store-load pairs) */
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/* Alternating store and load to the same address. */
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/* Tests store-load forwarding and memory subsystem throughput. */
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/* ===================================================================== */
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uart_printf("Bench 6: Load-store pairs (50 pairs = 100 instrs)\n");
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{
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volatile uint32_t mem_area[4];
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c0 = rdcycle();
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i0 = rdinstret();
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__asm__ volatile("addi t0, zero, 1\n"
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".rept 50\n"
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"sw t0, 0(%[addr])\n"
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"lw t0, 0(%[addr])\n"
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".endr\n"
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:
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: [addr] "r"(mem_area)
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: "t0", "memory");
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c1 = rdcycle();
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i1 = rdinstret();
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print_result(c1 - c0, i1 - i0);
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}
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/* ===================================================================== */
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/* Benchmark 7: Branch-heavy loop (200 iterations, 3 instrs/iter) */
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/* Tests branch prediction integration with OOO pipeline. */
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/* Good prediction allows the loop body to overlap across iterations. */
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/* ===================================================================== */
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uart_printf("Bench 7: Branch loop (200 iters, 3 instrs/iter)\n");
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c0 = rdcycle();
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i0 = rdinstret();
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__asm__ volatile("addi t0, zero, 200\n"
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"addi t1, zero, 0\n"
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"1:\n"
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"addi t1, t1, 1\n"
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"addi t0, t0, -1\n"
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"bne t0, zero, 1b\n"
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:
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:
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: "t0", "t1");
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c1 = rdcycle();
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i1 = rdinstret();
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print_result(c1 - c0, i1 - i0);
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/* ===================================================================== */
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/* Summary */
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/* ===================================================================== */
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uart_printf("\n============================================================\n");
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uart_printf(" Performance measurement complete.\n");
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uart_printf(" Compare Bench 1 vs 2 (ADD) and Bench 3 vs 4 (MUL)\n");
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uart_printf(" to see the IPC benefit of out-of-order execution.\n");
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uart_printf("============================================================\n\n");
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uart_printf("<<PASS>>\n");
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return 0;
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}

‎sw/apps/tomasulo_test/Makefile‎

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# Copyright 2026 Two Sigma Open Source, LLC
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# Makefile for Tomasulo Correctness Test
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# Tests hazard handling, OOO execution, and register renaming
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SRC_C := ../../lib/src/uart.c tomasulo_test.c
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include ../../common/common.mk

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