Add FU-CDB pipeline: adapter, ALU shim, MUL/DIV shim into tomasulo_wrapper

  Phase A: fu_cdb_adapter — one-deep holding register between FU and CDB
  arbiter. Combinational pass-through when granted same cycle, latches
  and re-presents otherwise. Includes formal properties and 11 cocotb
  tests. Standalone SymbiYosys config in formal/.

  Phase B: Add `pc` field to rs_dispatch_t / rs_issue_t so shims can
  compute AUIPC/JAL link addresses. Plumbed through RS, testbench
  wrappers, and cocotb interfaces/models.

  Phase C: int_alu_shim + fu_cdb_adapter integrated into
  tomasulo_wrapper. INT_RS issues internally through the ALU shim and
  adapter to CDB arbiter slot 0, replacing the external i_fu_complete[0]
  path. fu_ready gated by adapter back-pressure. All 26 wrapper tests
  updated (backward-compat CDB methods moved from FU_ALU to FU_MUL).

  Phase D: int_muldiv_shim integrated into tomasulo_wrapper. MUL_RS
  issues internally through the muldiv shim (standalone multiplier +
  divider instances) to two fu_cdb_adapters driving CDB arbiter slots
  1 and 2. Per-FU in-flight tracking with flush suppression. fu_ready
  gated by busy + both adapter pending signals. Tests updated: CDB
  backward-compat methods moved from FU_MUL to FU_MEM (slot 3),
  arbitration contention test uses external-only slots (MEM/FP_ADD/
  FP_DIV), MANUAL_CDB_RS_TYPES excludes MUL_RS.

  After this commit, CDB slots 0-2 are driven by internal FU pipelines
  (ALU, MUL, DIV). Slots 3-6 remain external (MEM, FP_ADD, FP_MUL,
  FP_DIV).

Author: adambagley

formal/fu_cdb_adapter.sby

@@ -0,0 +1,21 @@
+[tasks]
+bmc
+cover
+
+[options]
+bmc: mode bmc
+bmc: depth 8
+cover: mode cover
+cover: depth 12
+
+[engines]
+smtbmc boolector
+
+[script]
+read -formal -sv riscv_pkg.sv
+read -formal -sv fu_cdb_adapter.sv
+prep -top fu_cdb_adapter
+
+[files]
+../hw/rtl/cpu_and_mem/cpu/riscv_pkg.sv
+../hw/rtl/cpu_and_mem/cpu/tomasulo/fu_cdb_adapter/fu_cdb_adapter.sv

formal/tomasulo_wrapper.sby

@@ -19,6 +19,13 @@ read -sv reorder_buffer.sv
 read -sv register_alias_table.sv
 read -sv reservation_station.sv
 read -sv cdb_arbiter.sv
+read -sv fu_cdb_adapter.sv
+read -sv int_alu_shim.sv
+read -sv int_muldiv_shim.sv
+read -sv divider.sv
+read -sv dsp_tiled_multiplier_unsigned.sv
+read -sv multiplier.sv
+read -sv alu.sv
 read -formal -sv tomasulo_wrapper.sv
 prep -top tomasulo_wrapper
 
@@ -30,4 +37,11 @@ prep -top tomasulo_wrapper
 ../hw/rtl/cpu_and_mem/cpu/tomasulo/register_alias_table/register_alias_table.sv
 ../hw/rtl/cpu_and_mem/cpu/tomasulo/reservation_station/reservation_station.sv
 ../hw/rtl/cpu_and_mem/cpu/tomasulo/cdb_arbiter/cdb_arbiter.sv
+../hw/rtl/cpu_and_mem/cpu/tomasulo/fu_cdb_adapter/fu_cdb_adapter.sv
+../hw/rtl/cpu_and_mem/cpu/tomasulo/fu_shims/int_alu_shim.sv
+../hw/rtl/cpu_and_mem/cpu/tomasulo/fu_shims/int_muldiv_shim.sv
+../hw/rtl/cpu_and_mem/cpu/ex_stage/alu/divider.sv
+../hw/rtl/cpu_and_mem/cpu/ex_stage/dsp_tiled_multiplier_unsigned.sv
+../hw/rtl/cpu_and_mem/cpu/ex_stage/alu/multiplier.sv
+../hw/rtl/cpu_and_mem/cpu/ex_stage/alu/alu.sv
 ../hw/rtl/cpu_and_mem/cpu/tomasulo/tomasulo_wrapper/tomasulo_wrapper.sv

hw/rtl/cpu_and_mem/cpu/riscv_pkg.sv

@@ -1420,6 +1420,8 @@ package riscv_pkg;
     // CSR info
     logic [11:0]                      csr_addr;
     logic [4:0]                       csr_imm;
+    // Program counter (for ALU: AUIPC, JAL/JALR link address)
+    logic [XLEN-1:0]                  pc;
   } rs_dispatch_t;
 
   // RS issue signals (from RS to functional unit)
@@ -1443,6 +1445,8 @@ package riscv_pkg;
     // CSR info
     logic [11:0]                      csr_addr;
     logic [4:0]                       csr_imm;
+    // Program counter (for ALU: AUIPC, JAL/JALR link address)
+    logic [XLEN-1:0]                  pc;
   } rs_issue_t;
 
   // ---------------------------------------------------------------------------

hw/rtl/cpu_and_mem/cpu/tomasulo/fu_cdb_adapter/README.md

@@ -0,0 +1,22 @@
+# FU CDB Adapter
+
+One-deep holding register that sits between a functional unit and the CDB
+arbiter. Provides back-pressure signaling, zero-latency combinational
+pass-through when the arbiter grants immediately, and pipeline flush support.
+
+## Ports
+
+| Port | Dir | Type | Description |
+|------|-----|------|-------------|
+| `i_clk` | in | logic | Clock |
+| `i_rst_n` | in | logic | Active-low reset |
+| `i_fu_result` | in | `fu_complete_t` | FU result (level signal) |
+| `o_fu_complete` | out | `fu_complete_t` | To CDB arbiter |
+| `i_grant` | in | logic | CDB arbiter grant |
+| `o_result_pending` | out | logic | Back-pressure to RS |
+| `i_flush` | in | logic | Pipeline flush |
+
+## State Machine
+
+- **IDLE**: Pass-through from `i_fu_result` to `o_fu_complete`
+- **PENDING**: Output from held register, waiting for grant

hw/rtl/cpu_and_mem/cpu/tomasulo/fu_cdb_adapter/fu_cdb_adapter.f

@@ -0,0 +1,8 @@
+# FU CDB Adapter file list
+# One-deep holding register between FU output and CDB arbiter
+
+# Package dependency
+$(ROOT)/hw/rtl/cpu_and_mem/cpu/riscv_pkg.sv
+
+# Module
+$(ROOT)/hw/rtl/cpu_and_mem/cpu/tomasulo/fu_cdb_adapter/fu_cdb_adapter.sv