refactor(tomasulo): migrate payload storage from FFs to distributed RAM (LUTRAM)

  Move bulk data fields out of flip-flops into LUTRAM across three modules,
  keeping only control/CAM-scanned bits in registers:

  - reservation_station: 185-bit payload (op, imm, rm, branch_target,
    predicted_taken, predicted_target, is_fp_mem, mem_size, mem_signed,
    csr_addr, csr_imm, pc) into single sdp_dist_ram instance
    (write@dispatch, read@issue)

  - load_queue: 64-bit lq_data split into lo/hi mwp_dist_ram instances
    (2 write ports each: port 0 for cache-hit/forward/mem-response,
    port 1 for AMO completion; split enables FLD partial-word writes)

  - store_queue: 64-bit sq_data into duplicated sdp_dist_ram instances
    (shared CAM-resolved write, independent reads for forwarding scan
    and head writeback)

  Update .f filelists with RAM primitive dependencies.
  Update all three READMEs to reflect hybrid FF + LUTRAM storage strategy.

Author: adambagley

formal/load_queue.sby

@@ -13,13 +13,17 @@ smtbmc boolector
 
 [script]
 read -formal -sv riscv_pkg.sv
+read -sv sdp_dist_ram.sv
+read -sv mwp_dist_ram.sv
 read -sv load_unit.sv
 read -sv lq_l0_cache.sv
 read -formal -sv load_queue.sv
 prep -top load_queue
 
 [files]
 ../hw/rtl/cpu_and_mem/cpu/riscv_pkg.sv
+../hw/rtl/lib/ram/sdp_dist_ram.sv
+../hw/rtl/lib/ram/mwp_dist_ram.sv
 ../hw/rtl/cpu_and_mem/cpu/ma_stage/load_unit.sv
 ../hw/rtl/cpu_and_mem/cpu/tomasulo/load_queue/lq_l0_cache.sv
 ../hw/rtl/cpu_and_mem/cpu/tomasulo/load_queue/load_queue.sv

formal/reservation_station.sby

@@ -13,9 +13,11 @@ smtbmc boolector
 
 [script]
 read -formal -sv riscv_pkg.sv
+read -sv sdp_dist_ram.sv
 read -formal -sv reservation_station.sv
 prep -top reservation_station
 
 [files]
 ../hw/rtl/cpu_and_mem/cpu/riscv_pkg.sv
+../hw/rtl/lib/ram/sdp_dist_ram.sv
 ../hw/rtl/cpu_and_mem/cpu/tomasulo/reservation_station/reservation_station.sv

formal/store_queue.sby

@@ -13,9 +13,11 @@ smtbmc boolector
 
 [script]
 read -formal -sv riscv_pkg.sv
+read -sv sdp_dist_ram.sv
 read -formal -sv store_queue.sv
 prep -top store_queue
 
 [files]
 ../hw/rtl/cpu_and_mem/cpu/riscv_pkg.sv
+../hw/rtl/lib/ram/sdp_dist_ram.sv
 ../hw/rtl/cpu_and_mem/cpu/tomasulo/store_queue/store_queue.sv

hw/rtl/cpu_and_mem/cpu/tomasulo/load_queue/README.md

@@ -29,17 +29,20 @@ freed when their result is accepted by the CDB arbiter (via `fu_cdb_adapter`).
 
 ## Storage Strategy
 
-All fields in FFs (not LUTRAM/BRAM). 8 entries at ~116 bits each (~928 bits
-total). Rationale:
-
-- **CAM-style tag search**: Address update must find matching `rob_tag` across
-  all entries in parallel. RAM primitives only provide single-address reads.
-- **Per-entry invalidation**: Partial flush (branch misprediction) must clear
-  individual entries by age comparison in a single cycle.
-- **Parallel priority scan**: Issue selection reads all entries to find the
-  oldest ready candidate. RAM would require sequential iteration.
-- **8 entries**: Too small for BRAM (minimum 18 Kbit), marginal for LUTRAM.
-- Same rationale as reservation stations, which use FF arrays at depths 2-8.
+**Hybrid FF + LUTRAM.** Control and CAM-scanned fields remain in FFs; the
+64-bit `data` field is stored in split lo/hi `mwp_dist_ram` instances (32 bits
+each, 2 write ports).
+
+- **FFs**: `valid`, `rob_tag`, `is_fp`, `addr_valid`, `address`, `size`,
+  `sign_ext`, `is_mmio`, `fp64_phase`, `issued`, `data_valid`, `forwarded`.
+  These require parallel CAM-style tag search, per-entry invalidation on flush,
+  and parallel priority scan for issue selection.
+- **LUTRAM** (`mwp_dist_ram`, 2 write ports each, lo/hi split):
+  - Port 0: cache-hit fast path, SQ forwarding, or memory response (mutually
+    exclusive sources).
+  - Port 1: AMO completion (can overlap with port 0).
+  - Split into lo (bits 31:0) and hi (bits 63:32) for FLD two-phase partial
+    writes (phase 0 writes lo only, phase 1 writes hi only).
 
 ## Entry Structure
 
@@ -56,7 +59,7 @@ total). Rationale:
 | fp64_phase  | 1 bit   | FLD phase: 0=low word, 1=high word       |
 | issued      | 1 bit   | Sent to memory                           |
 | data_valid  | 1 bit   | Data received from memory/forward        |
-| data        | 64 bits | Loaded data (FLEN for FLD)               |
+| data        | 64 bits | Loaded data (FLEN for FLD) — in LUTRAM   |
 | forwarded   | 1 bit   | Data from store queue forward            |
 | **Total**   | **~116 bits** |                                    |
 
@@ -132,6 +135,16 @@ total). Rationale:
   flush, ordering, back-pressure, constrained random, LR/SC reservation,
   and AMO read-modify-write operations.
 
+## Dependencies
+
+| Module | Purpose |
+|--------|---------|
+| `riscv_pkg` | Type definitions |
+| `sdp_dist_ram` | Simple dual-port distributed RAM (used by `lq_l0_cache`) |
+| `mwp_dist_ram` | Multi-write-port distributed RAM for lq_data lo/hi LUTRAM |
+| `load_unit` | Byte/halfword extraction and sign extension |
+| `lq_l0_cache` | L0 data cache for OoO load hits |
+
 ## Files
 
 - `load_queue.sv` - Module implementation

hw/rtl/cpu_and_mem/cpu/tomasulo/load_queue/load_queue.f

@@ -1,9 +1,13 @@
 # Load Queue file list
-# Circular buffer tracking in-flight load instructions
+# Circular buffer tracking in-flight load instructions (hybrid FF + LUTRAM)
 
 # Package dependency
 $(ROOT)/hw/rtl/cpu_and_mem/cpu/riscv_pkg.sv
 
+# RAM primitives (lq_data LUTRAM)
+$(ROOT)/hw/rtl/lib/ram/sdp_dist_ram.sv
+$(ROOT)/hw/rtl/lib/ram/mwp_dist_ram.sv
+
 # Load unit (byte/halfword extraction and sign extension)
 $(ROOT)/hw/rtl/cpu_and_mem/cpu/ma_stage/load_unit.sv