File tree Expand file tree Collapse file tree
src/main/scala/viper/carbon/modules/impls Expand file tree Collapse file tree Original file line number Diff line number Diff line change @@ -401,7 +401,17 @@ class DefaultLoopModule(val verifier: Verifier) extends LoopModule with StmtComp
401401 w.info.getUniqueInfo[LoopInfo ] match {
402402 case Some (LoopInfo (Some (loopHeadId), _)) =>
403403 val invs = getLoopInvariants(loopHeadId)
404- val writtenVars = getWrittenVariables(loopHeadId) diff (w.body.transitiveScopedDecls.collect { case l : sil.LocalVarDecl => l } map (_.localVar))
404+ /** FIXME
405+ If loopToWrittenVars.get(loopHeadId).isEmpty evaluates to true, then it may be that the while loop may
406+ not be a natural loop in the CFG. In this case, it's not clear what the behaviour should be, so we just
407+ take the written variables via the AST (w.writtenVars).
408+ */
409+ val allWrittenVars = loopToWrittenVars.getOrElse(loopHeadId, w.writtenVars)
410+ /* FIXME
411+ * Not sure if the RHS of diff makes sense in the "normal" case where the written variables are
412+ * obtained from the LoopDetector. If syntactic and natural loops coincide, it might be fine.
413+ */
414+ val writtenVars = allWrittenVars diff (w.body.transitiveScopedDecls.collect { case l : sil.LocalVarDecl => l } map (_.localVar))
405415 (invs, writtenVars)
406416 case _ => sys.error(" While loop is not a loop head" )
407417 }
You can’t perform that action at this time.
0 commit comments