🔄 Show & Tell — Phase 34.2 EventDrivenProcessor: Asynchronous Neuromorphic Computation

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🔄 Phase 34.2 — EventDrivenProcessor

Event Processing Pipeline

                    ┌──────────────────────────────────────────────┐
                    │         EVENT-DRIVEN PROCESSING LOOP         │
                    └──────────────────────────────────────────────┘
                                         │
    ┌────────────────────────────────────┼────────────────────────────────┐
    │                                    ▼                                │
    │   ┌──────────┐   schedule    ┌──────────┐   heappop   ┌────────┐  │
    │   │ Neuron   │──────────────▶│ Min-Heap │────────────▶│Process │  │
    │   │ Models   │   O(log n)    │ Priority │   O(log n)  │ Event  │  │
    │   │ (34.1)   │               │  Queue   │             │        │  │
    │   └──────────┘               └──────────┘             └───┬────┘  │
    │        ▲                                                  │       │
    │        │                                                  ▼       │
    │        │    fire!       ┌──────────┐  integrate   ┌──────────┐   │
    │        │◀───────────────│Threshold │◀─────────────│ Target   │   │
    │        │                │  Check   │              │ Neurons  │   │
    │                         └──────────┘              └──────────┘   │
    │                              │ no fire                           │
    │                              ▼                                    │
    │                         [quiescent — no compute wasted]          │
    └──────────────────────────────────────────────────────────────────┘

Time-Stepped vs Event-Driven Comparison

Aspect	Time-Stepped	Event-Driven
Per-step cost	O(N) — scan ALL neurons	O(log n) — process ONE event
Sparse networks	Wastes 95%+ compute on silent neurons	Processes only active neurons
Temporal precision	Limited by dt (typically 0.1 ms)	Exact — events at continuous timestamps
Parallelism	Easy (same dt for all)	Requires causal ordering
Hardware mapping	Poor (global clock ≠ async chips)	Natural fit for Loihi/SpiNNaker
Determinism	Trivial (fixed ordering)	Requires tie-breaking protocol
Memory	O(N) neuron state always allocated	Lazy — allocate on first spike
Debugging	Inspect at any dt step	Event trace replay

When sparsity > 95% (typical cortical rates), event-driven is 10–100× faster.

Hardware Abstraction Layer

              ┌─────────────────────────────────────┐
              │   EventDrivenProcessorProtocol       │
              │   (unified API for all backends)     │
              └──────────────┬──────────────────────┘
                             │
            ┌────────────────┼────────────────────┐
            ▼                ▼                     ▼
    ┌──────────────┐ ┌──────────────┐  ┌──────────────────┐
    │   Software   │ │  Async       │  │   Hardware       │
    │   Backends   │ │  Backend     │  │   Emulators      │
    ├──────────────┤ ├──────────────┤  ├──────────────────┤
    │ PriorityQueue│ │ Lubachevsky  │  │ Loihi (128 core) │
    │ Processor    │ │ Relaxation   │  │ TrueNorth (4096) │
    │              │ │              │  │ SpiNNaker (48)   │
    │ TimeStepped  │ │ Local Virtual│  │                  │
    │ Processor    │ │ Time + GVT   │  │ Custom profiles  │
    └──────────────┘ └──────────────┘  └──────────────────┘

Sparse Activation — Why It Matters

Cortical neurons fire at ~1–5 Hz average. In a 1M-neuron network with 1ms simulation step:

Neurons active per ms:  ~1,000–5,000  (0.1–0.5% of total)
Neurons silent per ms: ~995,000–999,000

Time-stepped approach:  Process 1,000,000 neurons/ms  ← 99.5% wasted
Event-driven approach:  Process    ~5,000 events/ms   ← 200× speedup

Activity heatmap (1000 neurons, 100ms window):
Neuron   ░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░
  1-100  ░░░░░░██░░░░░░░░░░░░░░░░░░░░░░░░░░░█░░░░░░░░░░░░░░░
101-200  ░░░░░░░░░░░░██░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░
201-300  ░░█░░░░░░░░░░░░░░░░░░░░██░░░░░░░░░░░░░░░░░░░░░░░░░░
301-400  ░░░░░░░░░░░░░░░░█░░░░░░░░░░░░░░░░░░░░░░░░░█░░░░░░░░
  ...                    (vast majority = silent)
901-1000 ░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░██░░░░░░░░░░░░░░░░
         └────────── time (ms) ──────────────────────────────┘
  █ = spike event processed     ░ = quiescent (zero compute)

Performance Comparison (Projected)

Processor	10K Neurons	100K Neurons	1M Neurons
TimeSteppedProcessor	100K events/s	10K events/s	1K events/s
PriorityQueueProcessor	12M events/s	10M events/s	8M events/s
AsynchronousProcessor (4-way)	6M events/s	5M events/s	4M events/s
HardwareEmulator (Loihi)	50M events/s	40M events/s	30M events/s

PriorityQueueProcessor scales sub-linearly because heap operations are O(log n), while TimeStepped degrades linearly with neuron count.

Hardware Energy Estimates (Per 1M Spikes)

Platform	Energy (mJ)	Latency (ms)	Notes
Loihi (128-core)	23.6	0.05	On-chip STDP learning
TrueNorth (4096-core)	26.0	0.001	Binary weights, tick-based
SpiNNaker (48-core)	50.0	0.5	ARM968, packet-switched
GPU (CUDA, A100)	~500	0.01	Dense compute, high bandwidth
CPU (software sim)	~2000	10.0	Sequential, cache-limited

Neuromorphic hardware achieves 20–80× energy reduction over GPU for spike-sparse workloads.

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Open Questions

1. Tie-breaking strategy: When multiple events share the same timestamp, should we use FIFO (insertion order) or neuron-ID ordering? FIFO is simpler but neuron-ID may give more reproducible cross-platform results.

2. Batch processing: Should process_next() handle all same-timestamp events atomically, or should the caller loop? Atomic batching reduces call overhead but complicates the return type.

3. Memory-mapped queues: For >10M pending events, should we spill the heap to memory-mapped files (mmap) to avoid Python's GC pressure?

4. Async integration: Should the AsynchronousProcessor use asyncio, multiprocessing, or threading? The GIL favors multiprocessing for CPU-bound work, but asyncio integrates better with I/O-bound orchestration layers.

5. Hardware fidelity: How closely should the emulator match published chip behavior? Cycle-accurate emulation is expensive; instruction-level approximation may suffice for algorithm development.

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Links: Issue #707 · Phase 34.1 SpikingNeuronModel #697