Q&A — Phase 35.5 QuantumClassicalOrchestrator

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Q&A — Phase 35.5 QuantumClassicalOrchestrator

Q1: How does hybrid backpropagation work when quantum and classical layers are interleaved?

A: The orchestrator treats quantum layers as differentiable functions within the PyTorch/JAX autograd framework. During the forward pass, classical layers compute normally while quantum layers execute circuits on the backend and return expectation values. During the backward pass:

1. Classical gradients propagate normally via autograd.
2. At quantum layer boundaries, the parameter-shift rule computes dL/d(theta_i) for each quantum parameter.
3. For input gradients (dL/dx flowing through the quantum layer), we use the adjoint differentiation method on simulators or finite-difference approximation on hardware.
4. The chain rule connects quantum and classical gradients: dL/d(theta) = dL/d() * d()/d(theta).

This creates a seamless gradient flow across the hybrid architecture. The main overhead is that each quantum parameter requires 2 additional circuit evaluations for gradient estimation, making the backward pass cost O(2p) circuit runs for p quantum parameters. We mitigate this with batched execution and gradient caching.

Q2: How optimal is the SABRE qubit routing algorithm?

A: SABRE (Li et al. 2019) is a heuristic algorithm that is not guaranteed to find the optimal mapping, but performs well in practice:

• Optimality gap: Typically within 10-20% of the optimal SWAP count for circuits with 10-50 qubits on grid topologies. The gap increases for highly connected interaction graphs on sparsely connected hardware.
• Time complexity: O(|G| * d * t) where |G| is number of gates, d is coupling graph diameter, and t is number of trials. Typically runs in milliseconds for practical circuits.
• Alternatives we support: Token swapping (exact for permutation routing), A-star search (optimal but exponential), and noise-aware routing (considers gate error rates, not just distance).
• Improvement strategies: Multiple random restarts (default: 20 trials), reverse traversal refinement, and post-routing SWAP cancellation.

For critical circuits where SWAP overhead significantly impacts results, users can switch to the exact A-star router for small circuits (fewer than 15 qubits) or provide manual qubit mappings.

Q3: How does noise-aware compilation differ from standard compilation?

A: Standard compilation minimizes gate count or circuit depth. Noise-aware compilation additionally considers:

1. Per-gate error rates: Route two-qubit gates through physical qubit pairs with lowest CNOT error rates, even if this increases SWAP count slightly. The objective becomes minimizing expected total error, not SWAP count.
2. Qubit coherence times: Assign qubits with longer T1/T2 to logical qubits that are active longest in the circuit. Idle qubits on short-T1 physical qubits decohere faster.
3. Crosstalk avoidance: Avoid simultaneous parallel gates on qubit pairs known to exhibit crosstalk. This may increase depth but improves fidelity.
4. Readout error assignment: Map frequently-measured logical qubits to physical qubits with lowest readout error.
5. Calibration recency: Prefer qubit pairs whose calibration data is most recent, as error rates drift over time.

The noise-aware compiler requires a device calibration profile (automatically fetched from hardware providers) and solves a weighted optimization problem balancing depth, gate count, and expected fidelity.

Q4: How do we standardize benchmarks for fair quantum-classical comparison?

A: Benchmark standardization follows these principles:

1. Problem equivalence: Both quantum and classical solvers receive identical problem instances (same graph, same Hamiltonian, same dataset).
2. Time budget fairness: Wall-clock time includes all overhead: compilation, data transfer, queue wait time (for cloud quantum), and post-processing. Classical baselines run on equivalent-cost hardware (a single GPU matching the quantum access cost).
3. Statistical rigor: Each benchmark runs 30+ repetitions with different random seeds. Results are compared using paired t-tests with Bonferroni correction for multiple comparisons.
4. Scaling study: Benchmarks are run at multiple problem sizes (n = 4, 8, 12, 16, 20 qubits for QAOA; d = 2, 4, 8, 16 features for QML) to identify crossover points.
5. Baseline selection: Classical baselines use state-of-the-art algorithms, not strawman implementations. For Max-Cut: Goemans-Williamson SDP relaxation. For molecular simulation: CCSD(T) with extrapolation. For classification: RBF-SVM with grid-searched hyperparameters.
6. Reproducibility: All benchmark configurations, random seeds, hardware calibration snapshots, and raw results are version-controlled.

Q5: How should quantum advantage claims be verified?

A: We follow a rigorous verification protocol:

1. Define the advantage claim precisely: Is it computational speedup, solution quality improvement, or sample efficiency? On which problem class and at what size?
2. Rule out classical improvements: Before claiming advantage, verify that no classical algorithm (including recently published ones) can match the quantum result. We maintain a classical algorithm registry with performance profiles.
3. Account for all overhead: Include circuit compilation, communication latency, error mitigation cost, and measurement overhead. A quantum algorithm that is 10x faster at circuit execution but requires 100x overhead in error mitigation has no net advantage.
4. Statistical significance: Advantage must be demonstrated with p < 0.01 on held-out test instances, not just training instances.
5. Scaling evidence: Show that the advantage grows (or at least persists) with problem size. An advantage at n=6 that disappears at n=12 is not meaningful.
6. Peer review: All advantage claims are flagged for manual review before being reported externally.

The AdvantageReport includes mandatory caveats: "simulator only," "specific problem instance," "excludes compilation overhead," etc.

Q6: How does the orchestrator integrate with existing ASI-Build modules?

A: Integration follows the standard ASI-Build module interface pattern:

• Input adapters: Convert ASI-Build data structures (tensors, graphs, knowledge representations) into quantum-compatible formats (Pauli Hamiltonians, classical data vectors, adjacency matrices).
• Output adapters: Convert quantum results (expectation values, measurement distributions, optimized parameters) back into ASI-Build formats.
• Pipeline nodes: The orchestrator registers as a pipeline node that can be inserted into any ASI-Build processing chain. It accepts configuration specifying which sub-components to use (VQE, QAOA, kernel SVM, etc.).
• Resource negotiation: The orchestrator requests quantum resources (qubits, shots, time) through ASI-Build's resource management layer (Phase 28 Cognitive Load Balancer), enabling graceful degradation to classical fallback when quantum resources are unavailable.
• Logging and monitoring: All quantum executions are logged with circuit metadata, execution parameters, and results, integrating with Phase 16's PerformanceProfiler for end-to-end performance analysis.

Q7: How does the system scale to 100+ qubit circuits?

A: Scaling to 100+ qubits requires strategies across all components:

1. Circuit construction (35.1): DAG representation scales linearly in gate count. Optimization passes use local windows to avoid quadratic blowup.
2. Simulation: Full statevector simulation is impossible beyond ~35 qubits (2^35 amplitudes = 256 GB). We use tensor network simulation (MPS/MPO) for structured circuits, Clifford simulation for stabilizer circuits, and shot-based simulation with importance sampling.
3. Variational optimization (35.2): Barren plateaus become severe at 100+ qubits. Mitigation: local cost functions, shallow ansatze, symmetry-preserving circuits, and layerwise training.
4. Qubit routing: SABRE scales well but routing overhead increases. For 100+ qubits on sparse topologies, we use hierarchical routing: partition the circuit into blocks, route blocks independently, then stitch.
5. Hardware execution: Cloud quantum providers currently offer 50-1000+ qubits. The orchestrator handles job submission, queue management, result retrieval, and error mitigation at scale.
6. Memory management: Density matrices and full unitaries are infeasible. All operations use statevector or tensor network representations with lazy evaluation and streaming computation.

The orchestrator provides a scalability report estimating resource requirements (memory, time, shots) for a given circuit before execution, enabling informed decisions about feasibility.