The current SPRs for CICE4 and CICE5 hard-code the processor decomposition and grid for the build. This is immediately problematic for users who which to debug their applications, as debuggers often have limits on the number of processes a task can have (e.g. Linaro Forge on NCI Gadi has a maximum of 256 processors for DDT and Map). It also makes build optimisation a pain, as every build has to modify the SPR. The configuration should be settable via the spack.yaml.
The current SPRs for CICE4 and CICE5 hard-code the processor decomposition and grid for the build. This is immediately problematic for users who which to debug their applications, as debuggers often have limits on the number of processes a task can have (e.g. Linaro Forge on NCI Gadi has a maximum of 256 processors for DDT and Map). It also makes build optimisation a pain, as every build has to modify the SPR. The configuration should be settable via the
spack.yaml.