feat(MMIOBridge): support Svpbmt on CHI MemAttr

[Kumonda221-CrO3]

• Added user field memType_NC to recognize NC type configured by Svpbmt, mapped to Non-cacheable Bufferable.

• Memory attributes other than NC are still mapped to Device nRnE in CHI specification.

[Kumonda221-CrO3]

NOTICE

DO NOT set bufferableNC = true when needRR = false, since the ordering between NC and IO described in SvPBMT was maintained by fence iorw, iorw. And alias with NC and IO must not cause loss of coherency due to SvPBMT, which was NOT guaranteed by CHI specification in which case obtaining different EWA from different agents.

1. For Memory backend, the observability of possible weakly-ordered intermediate states were determined
   by the core (the processor pipeline, store buffer, etc.) because there is no ordering guarantee from HN.
2. For Device backend, the observability of possible weakly-ordered intermediate states were determined by the HN (Home Node) on bus with Endpoint Ordering.

Ordering and MemAttr

MM = Main Memory, NC = Non-cacheable, IO = Device I/O

• When bufferableNC configured to false

  PMA	PBMT	Memory Type
  MM	NC	Non-cacheable Non-bufferable
  MM	IO	Non-cacheable Non-bufferable
  NC/IO	NC	Device nRnE (no reorder, no early acknowlegment)
  NC/IO	IO	Device nRnE (no reorder, no early acknowlegment)

• when bufferableNC configured to true

  PMA	PBMT	Memory Type
  MM	NC	Non-cacheable Bufferable
  MM	IO	Non-cacheable Bufferable
  NC/IO	NC	Device nRE (no reorder, early acknowlegment)
  NC/IO	IO	Device nRnE (no reorder, no early acknowlegment)