feat(L2 cache): l2 release to lqRAR using CHI-ports txreq, txrsp, txdat

src/main/scala/coupledL2/tl2chi/Slice.scala

@@ -25,7 +25,8 @@ import coupledL2._
 import coupledL2.prefetch.PrefetchIO
 import utility.MemReqSource
 
-class OuterBundle(implicit p: Parameters) extends DecoupledPortIO with BaseOuterBundle
+// class OuterBundle(implicit p: Parameters) extends DecoupledPortIO with BaseOuterBundle
+class OuterBundle(implicit p: Parameters) extends DecoupledPortIO_withAddr with BaseOuterBundle
 
 class Slice()(implicit p: Parameters) extends BaseSlice[OuterBundle]
   with HasCoupledL2Parameters
@@ -74,10 +75,12 @@ class Slice()(implicit p: Parameters) extends BaseSlice[OuterBundle]
 
   txdat.io.in <> mainPipe.io.toTXDAT
   txdat.io.pipeStatusVec := status_vec_toTX
+  txdat.io.sliceId := io.sliceId
 
   txrsp.io.pipeRsp <> mainPipe.io.toTXRSP
   txrsp.io.mshrRsp <> mshrCtl.io.toTXRSP
   txrsp.io.pipeStatusVec := status_vec_toTX
+  txrsp.io.sliceId := io.sliceId
 
   rxsnp.io.msInfo := mshrCtl.io.msInfo
 

src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala

@@ -71,6 +71,7 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
     val io_chi = IO(new PortIO)
     val io_nodeID = IO(Input(UInt()))
     val io_cpu_halt = Option.when(cacheParams.enableL2Flush) (IO(Input(Bool())))
+    val io_l2_release = IO(Vec(2, ValidIO(UInt(ADDR_WIDTH.W))))
 
     // Check port width
     require(io_chi.tx.rsp.getWidth == io_chi.rx.rsp.getWidth);
@@ -137,11 +138,22 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
 
         // TXRSP
         val txrsp = Wire(DecoupledIO(new CHIRSP))
-        fastArb(slices.map(_.io.out.tx.rsp), txrsp, Some("txrsp"))
+        val txrsp_withAddr = Wire(DecoupledIO(new CHIRSP_withAddr))
+        fastArb(slices.map(_.io.out.tx.rsp), txrsp_withAddr, Some("txrsp"))
+        txrsp.bits := CHIRSP_withAddr.toCHIRSP(txrsp_withAddr.bits)
+        txrsp.valid := txrsp_withAddr.valid
+        txrsp_withAddr.ready := txrsp.ready
 
         // TXDAT
+        val mmio_io_tx_dat_withAddr, txdat_withAddr = Wire(DecoupledIO(new CHIDAT_withAddr))
+        mmio_io_tx_dat_withAddr.valid := mmio.io.tx.dat.valid
+        mmio_io_tx_dat_withAddr.bits := CHIDAT_withAddr(mmio.io.tx.dat.bits, 0.U)
+        mmio.io.tx.dat.ready := mmio_io_tx_dat_withAddr.ready
+        fastArb(slices.map(_.io.out.tx.dat) :+ mmio_io_tx_dat_withAddr, txdat_withAddr, Some("txdat"))
         val txdat = Wire(DecoupledIO(new CHIDAT))
-        fastArb(slices.map(_.io.out.tx.dat) :+ mmio.io.tx.dat, txdat, Some("txdat"))
+        txdat.bits := CHIDAT_withAddr.toCHIDAT(txdat_withAddr.bits)
+        txdat.valid := txdat_withAddr.valid
+        txdat_withAddr.ready := txdat.ready
 
         // RXSNP
         val rxsnp = Wire(DecoupledIO(new CHISNP))
@@ -268,6 +280,24 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
           Cat(slices.zipWithIndex.map { case (s, i) => s.io.l2FlushDone.getOrElse(false.B)}).andR && io_cpu_halt.getOrElse(false.B)
         }
 
+        // Release signals to loadQueueRAR
+        // TXREQ
+        val release_txreq_valid = txreq.fire && (txreq.bits.opcode === Evict ||
+                                  txreq.bits.opcode === CleanInvalid || txreq.bits.opcode === MakeInvalid ||
+                                  txreq.bits.opcode === WriteBackFull || txreq.bits.opcode === WriteEvictOrEvict)
+        io_l2_release(0).valid := RegNext(release_txreq_valid)
+        require(txreq.bits.addr.getWidth == io_l2_release(0).bits.getWidth)
+        io_l2_release(0).bits := RegEnable(txreq.bits.addr, release_txreq_valid)
+        // TXRSP
+        val release_txrsp_valid = txrsp.fire && isSnpToN(txrsp.bits.opcode)
+        val release_txrsp_addr = txrsp_withAddr.bits.addr
+        // TXDAT
+        val release_txdat_valid = txdat.fire && isSnpToN(txdat.bits.opcode)
+        val release_txdat_addr = txdat_withAddr.bits.addr
+        io_l2_release(1).valid := RegNext(release_txrsp_valid || release_txdat_valid)
+        io_l2_release(1).bits := RegEnable(Mux(release_txrsp_valid, release_txrsp_addr, release_txdat_addr), release_txrsp_valid || release_txdat_valid)
+        assert(!(release_txrsp_valid && release_txdat_valid), "L2 release_txrsp_valid and release_txdat_valid should not be true at the same time")
+
         /**
           * performance counters
           */

src/main/scala/coupledL2/tl2chi/TXDAT.scala

@@ -33,10 +33,12 @@ class TXDATBlockBundle(implicit p: Parameters) extends TXBlockBundle {
 class TXDAT(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
   val io = IO(new Bundle() {
     val in = Flipped(DecoupledIO(new TaskWithData()))
-    val out = DecoupledIO(new CHIDAT())
+    val out = DecoupledIO(new CHIDAT_withAddr)
 
     val pipeStatusVec = Flipped(Vec(5, ValidIO(new PipeStatusWithCHI)))
     val toReqArb = Output(new TXDATBlockBundle)
+
+    val sliceId = Input(UInt(bankBits.W))
   })
 
   assert(!io.in.valid || io.in.bits.task.toTXDAT, "txChannel is wrong for TXDAT")
@@ -98,7 +100,8 @@ class TXDAT(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
   val (beat, next_beatsOH) = getBeat(data, beatsOH)
 
   io.out.valid := taskValid
-  io.out.bits := toCHIDATBundle(taskR.task, beat, beatsOH)
+  io.out.bits := CHIDAT_withAddr(toCHIDATBundle(taskR.task, beat, beatsOH), 
+                                  restoreAddressUInt(taskR.task.toCHIREQBundle().addr, io.sliceId))
   // for TXDAT, WriteBack & SnpX will not allow CompData with NDERR
   io.out.bits.respErr := Mux(taskR.task.corrupt, RespErrEncodings.DERR, RespErrEncodings.OK)
 

src/main/scala/coupledL2/tl2chi/TXRSP.scala

@@ -34,18 +34,20 @@ class TXRSP(implicit p: Parameters) extends TL2CHIL2Module {
     // val in = Flipped(DecoupledIO(new TaskBundle()))
     val pipeRsp = Flipped(DecoupledIO(new TaskBundle))
     val mshrRsp = Flipped(DecoupledIO(new CHIRSP()))
-    val out = DecoupledIO(new CHIRSP())
+    val out = DecoupledIO(new CHIRSP_withAddr)
 
     val pipeStatusVec = Flipped(Vec(5, ValidIO(new PipeStatusWithCHI)))
     val toReqArb = Output(new TXRSPBlockBundle)
+
+    val sliceId = Input(UInt(bankBits.W))
   })
 
   assert(!io.pipeRsp.valid || io.pipeRsp.bits.toTXRSP, "txChannel is wrong for TXRSP")
   assert(io.pipeRsp.ready, "TXRSP should never be full")
   require(chiOpt.isDefined)
 
   // TODO: an mshrsAll-entry queue is too much, evaluate for a proper size later
-  val queue = Module(new Queue(new CHIRSP, entries = mshrsAll, flow = false))
+  val queue = Module(new Queue(new CHIRSP_withAddr, entries = mshrsAll, flow = false))
 
   // Back pressure logic from TXRSP
   val queueCnt = queue.io.count
@@ -73,7 +75,10 @@ class TXRSP(implicit p: Parameters) extends TL2CHIL2Module {
   queue.io.deq.ready := io.out.ready
 
   queue.io.enq.valid := io.pipeRsp.valid || io.mshrRsp.valid && !noSpaceForSinkBReq && !noSpaceForMSHRReq
-  queue.io.enq.bits := Mux(io.pipeRsp.valid, toCHIRSPBundle(io.pipeRsp.bits), io.mshrRsp.bits)
+  queue.io.enq.bits := Mux(io.pipeRsp.valid,
+                           CHIRSP_withAddr(toCHIRSPBundle(io.pipeRsp.bits), 
+                                           restoreAddressUInt(io.pipeRsp.bits.toCHIREQBundle().addr, io.sliceId)),
+                           CHIRSP_withAddr(io.mshrRsp.bits, 0.U)) // from mshrRsp is only compAck? set addr to 0.U (don't care)
 
   io.pipeRsp.ready := true.B
   io.mshrRsp.ready := !io.pipeRsp.valid && !noSpaceForSinkBReq && !noSpaceForMSHRReq

src/main/scala/coupledL2/tl2chi/chi/LinkLayer.scala

@@ -74,6 +74,12 @@ class DecoupledDownwardsLinkIO(implicit p: Parameters) extends Bundle {
   val dat = DecoupledIO(new CHIDAT)
 }
 
+class DecoupledDownwardsLinkIO_withAddr(implicit p: Parameters) extends Bundle {
+  val req = DecoupledIO(new CHIREQ)
+  val rsp = DecoupledIO(new CHIRSP_withAddr)
+  val dat = DecoupledIO(new CHIDAT_withAddr)
+}
+
 class DecoupledUpwardsLinkIO(implicit p: Parameters) extends Bundle {
   val rsp = DecoupledIO(new CHIRSP)
   val dat = DecoupledIO(new CHIDAT)
@@ -102,6 +108,11 @@ class DecoupledPortIO(implicit p: Parameters) extends Bundle {
   val rx = Flipped(new DecoupledUpwardsLinkIO)
 }
 
+class DecoupledPortIO_withAddr(implicit p: Parameters) extends Bundle {
+  val tx = new DecoupledDownwardsLinkIO_withAddr
+  val rx = Flipped(new DecoupledUpwardsLinkIO)
+}
+
 class DecoupledNoSnpPortIO(implicit p: Parameters) extends Bundle {
   val tx = new DecoupledDownwardsNoSnpLinkIO
   val rx = Flipped(new DecoupledUpwardsNoSnpLinkIO)

src/main/scala/coupledL2/tl2chi/chi/Message.scala

@@ -581,3 +581,51 @@ class CHIRSP(implicit p: Parameters) extends CHIBundle {
   val traceTag = Bool()
   /* MSB */
 }
+
+// CHIRSP_withAddr is CHIRSP with an additional 'addr' field which is used for release to loadQueueRAR
+class CHIRSP_withAddr(implicit p: Parameters) extends CHIRSP {
+  val addr = UInt(ADDR_WIDTH.W)
+}
+object CHIRSP_withAddr{
+  def apply(chirsp: CHIRSP, addr: UInt)(implicit p: Parameters): CHIRSP_withAddr = {
+    val chirsp_with_addr = Wire(new CHIRSP_withAddr)
+    chirsp.elements.foreach { case (name, data) =>
+      chirsp_with_addr.elements(name) := data
+    }
+    chirsp_with_addr.addr := addr
+    chirsp_with_addr
+  }
+  def toCHIRSP(chirsp_with_addr: CHIRSP_withAddr)(implicit p: Parameters): CHIRSP = {
+    val chirsp = Wire(new CHIRSP)
+    chirsp_with_addr.elements.foreach { case (name, data) =>
+      if (chirsp.elements.contains(name)) {
+        chirsp.elements(name) := data
+      }
+    }
+    chirsp
+  }
+}
+
+// CHIDAT_withAddr is CHIDAT with an additional 'addr' field which is used for release to loadQueueRAR
+class CHIDAT_withAddr(implicit p: Parameters) extends CHIDAT {
+  val addr = UInt(ADDR_WIDTH.W)
+}
+object CHIDAT_withAddr{
+  def apply(chidat: CHIDAT, addr: UInt)(implicit p: Parameters): CHIDAT_withAddr = {
+    val chidat_with_addr = Wire(new CHIDAT_withAddr)
+    chidat.elements.foreach { case (name, data) =>
+      chidat_with_addr.elements(name) := data
+    }
+    chidat_with_addr.addr := addr
+    chidat_with_addr
+  }
+  def toCHIDAT(chidat_with_addr: CHIDAT_withAddr)(implicit p: Parameters): CHIDAT = {
+    val chidat = Wire(new CHIDAT)
+    chidat_with_addr.elements.foreach { case (name, data) =>
+      if (chidat.elements.contains(name)) {
+        chidat.elements(name) := data
+      }
+    }
+    chidat
+  }
+}