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chore(TestTop): support for L2 power down #485

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chore(TestTop): support for L2 power down #485

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cdd6994
chore(TestTop): support for L2 power down
Kumonda221-CrO3 Apr 1, 2026
89d21a4
feat(TestTop): add link and power down ports
Kumonda221-CrO3 Apr 3, 2026
f661785
feat(TestTop): support for Seperate Reset
Kumonda221-CrO3 Apr 7, 2026
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24 changes: 23 additions & 1 deletion src/test/scala/chi/TestTop.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -168,6 +168,16 @@ class TestTop_CHIL2(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, ext
val nodeId = Input(UInt(NODEID_WIDTH.W))
}))

val io_powerdown = IO(Vec(numCores, new Bundle {
val flushAll = Input(Bool())
val flushAllDone = Output(Bool())
val cpuHalt = Input(Bool())
}))

val io_linkdown = IO(Vec(numCores, Output(Bool())))

val io_resetsep = IO(Vec(numCores, Input(Bool())))

l2_nodes.zipWithIndex.foreach { case (l2, i) =>

if (!cacheParams.FPGAPlatform && cacheParams.enableCHILog) {
Expand Down Expand Up @@ -196,6 +206,15 @@ class TestTop_CHIL2(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, ext
l2.module.io_nodeID := io(i).nodeId
l2.module.io.debugTopDown := DontCare
l2.module.io.l2_tlb_req <> DontCare
l2.module.io.l2Flush.foreach(_ := io_powerdown(i).flushAll)
io_powerdown(i).flushAllDone := l2.module.io.l2FlushDone.getOrElse(false.B)
l2.module.io_cpu_halt.foreach(_ := io_powerdown(i).cpuHalt)

l2.module.reset := io_resetsep(i) || reset.asBool

io_linkdown(i) := !l2.module.io_chi.syscoreq && !l2.module.io_chi.syscoack &&
!l2.module.io_chi.tx.linkactivereq && !l2.module.io_chi.tx.linkactiveack &&
!l2.module.io_chi.rx.linkactivereq && !l2.module.io_chi.rx.linkactiveack
}
}
}
Expand Down Expand Up @@ -237,7 +256,10 @@ object TestTopCHIHelper {
enableDataECC = true,

// using external RN-F SAM
sam = Seq(AddressSet.everything -> 0)
sam = Seq(AddressSet.everything -> 0),

// L2 flush all
enableL2Flush = true
)
case CHIIssue => issue
case EnableCHI => true
Expand Down
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