timing(RequestBuffer, MMIOBridge): optimize timing#486
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timing(RequestBuffer, MMIOBridge): optimize timing#486
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In the original design, when `io.out` and a buffer entry have the same set, backpressure will be applied to issueArb, preventing that buffer entry from participating in issueArb arbitration. However, at the same time, when the buffer updates its `rdy` logic, if that buffer entry and `io.out` shares the same set, the `rdy` bit will be pulled low. As a result, even if that entry participates in issueArb arbitration and is successfully selected, it could not be dequeued from chosenQ and will instead be canceled. This commit removes the backpressure logic on issueArb to improve timing.
linjuanZ
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`aMergeTask` (i.e., when a demand access arrives at L2 and a prefetch with the same address is being processed) can only merge the demand access if the prefetch has not yet performed refill. A special case occurs when a prefetch merges a demand access at the exact cycle it already receives Grant and is about to issue a refill request. This causes the signals in the refill request to depend on the outcome of mergeA logics. This commit tightens the condition for mergeA, allowing it only when refill request has not yet been issued, thereby breaking the combinational logic chain to improve timing. It should be noted that this modification may have a slight impact on performance in some corner cases.
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Kumonda221-CrO3
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Apr 9, 2026
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