fix(SinkA): cmoAll FSM returns to IDLE when finished

.github/workflows/main.yml

@@ -6,9 +6,9 @@ name: CI
 on:
   # Triggers the workflow on push or pull request events but only for the main branch
   push:
-    branches: [ master, chi-coupledl2 ]
+    branches: [ master, kunminghu-v2 ]
   pull_request:
-    branches: [ master, chi-coupledl2 ]
+    branches: [ master, kunminghu-v2 ]
 
   # Allows you to run this workflow manually from the Actions tab
   workflow_dispatch:
@@ -67,12 +67,14 @@ jobs:
           sudo bash install-verilator.sh
 
       - name: Setup Scala
-        uses: olafurpg/setup-scala@v10
+        uses: olafurpg/setup-scala@v11
+        with:
+          java-version: [email protected]
 
       - name: Setup Mill
         uses: jodersky/[email protected]
         with:
-          mill-version: 0.11.1
+          mill-version: 0.12.3
 
       # - name: Check scalafmt
       #   run: make checkformat

.mill-version

@@ -1 +1 @@
-0.11.1
+0.12.3

build.sc

@@ -5,9 +5,8 @@ import os.Path
 import publish._
 import $file.common
 import $file.`rocket-chip`.common
-import $file.`rocket-chip`.common
 import $file.`rocket-chip`.cde.common
-import $file.`rocket-chip`.hardfloat.build
+import $file.`rocket-chip`.hardfloat.common
 
 val defaultScalaVersion = "2.13.15"
 
@@ -16,7 +15,9 @@ def defaultVersions = Map(
   "chisel-plugin" -> ivy"org.chipsalliance:::chisel-plugin:7.0.0"
 )
 
-trait HasChisel extends ScalaModule {
+val pwd = os.Path(sys.env("MILL_WORKSPACE_ROOT"))
+
+trait HasChisel extends SbtModule {
   def chiselModule: Option[ScalaModule] = None
 
   def chiselPluginJar: T[Option[PathRef]] = None
@@ -37,18 +38,24 @@ trait HasChisel extends ScalaModule {
 
 object rocketchip extends `rocket-chip`.common.RocketChipModule with HasChisel {
 
-  val rcPath = os.pwd / "rocket-chip"
+  val rcPath = pwd / "rocket-chip"
   override def millSourcePath = rcPath
 
   def mainargsIvy = ivy"com.lihaoyi::mainargs:0.7.0"
 
   def json4sJacksonIvy = ivy"org.json4s::json4s-jackson:4.0.7"
 
-  object macros extends `rocket-chip`.common.MacrosModule with HasChisel {
+  object macros extends `rocket-chip`.common.MacrosModule with SbtModule {
+
+    def scalaVersion: T[String] = T(defaultScalaVersion)
+
     def scalaReflectIvy = ivy"org.scala-lang:scala-reflect:${scalaVersion}"
   }
 
-  object cde extends `rocket-chip`.cde.common.CDEModule with HasChisel {
+  object cde extends `rocket-chip`.cde.common.CDEModule with ScalaModule {
+
+    def scalaVersion: T[String] = T(defaultScalaVersion)
+
     override def millSourcePath = rcPath / "cde" / "cde"
   }
 
@@ -64,8 +71,8 @@ object rocketchip extends `rocket-chip`.common.RocketChipModule with HasChisel {
 
 }
 
-object utility extends SbtModule with HasChisel {
-  override def millSourcePath = os.pwd / "utility"
+object utility extends HasChisel {
+  override def millSourcePath = pwd / "utility"
 
   override def moduleDeps = super.moduleDeps ++ Seq(rocketchip)
 
@@ -74,14 +81,14 @@ object utility extends SbtModule with HasChisel {
   )
 }
 
-object huancun extends SbtModule with HasChisel {
-  override def millSourcePath = os.pwd / "HuanCun"
+object huancun extends HasChisel {
+  override def millSourcePath = pwd / "HuanCun"
   override def moduleDeps = super.moduleDeps ++ Seq(
     rocketchip, utility
   )
 }
 
-object CoupledL2 extends SbtModule with HasChisel with millbuild.common.CoupledL2Module {
+object CoupledL2 extends HasChisel with $file.common.CoupledL2Module {
 
   override def millSourcePath = millOuterCtx.millSourcePath
 
@@ -91,7 +98,7 @@ object CoupledL2 extends SbtModule with HasChisel with millbuild.common.CoupledL
 
   def huancunModule: ScalaModule = huancun
 
-  object test extends SbtModuleTests with TestModule.ScalaTest
+  object test extends SbtTests with TestModule.ScalaTest
 
   override def scalacOptions = super.scalacOptions() ++ Agg("-deprecation", "-feature")
 

src/main/scala/coupledL2/SinkA.scala

@@ -188,6 +188,11 @@ class SinkA(implicit p: Parameters) extends L2Module {
   when (stateVal === sWAITMSHR && !mshrValid) {
     state.foreach { _ := sCMOREQ }
   }
+  when (stateVal === sDONE && !l2Flush) {
+    state.foreach { _ := sIDLE }
+    set.foreach { _ := 0.U }
+    way.foreach { _ := 0.U }
+  }
 
   // Performance counters
   // num of reqs

src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala

@@ -70,7 +70,7 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
 
     val io_chi = IO(new PortIO)
     val io_nodeID = IO(Input(UInt()))
-    val io_cpu_halt = Option.when(cacheParams.enableL2Flush) (IO(Input(Bool())))
+    val io_cpu_wfi = Option.when(cacheParams.enableL2Flush) (IO(Input(Bool())))
 
     // Check port width
     require(io_chi.tx.rsp.getWidth == io_chi.rx.rsp.getWidth);
@@ -265,7 +265,7 @@ class TL2CHICoupledL2(implicit p: Parameters) extends CoupledL2Base {
         linkMonitor.io.nodeID := io_nodeID
         /* exit coherency when: l2 flush of all slices is done and core is in WFI state */
         linkMonitor.io.exitco.foreach { _ :=
-          Cat(slices.zipWithIndex.map { case (s, i) => s.io.l2FlushDone.getOrElse(false.B)}).andR && io_cpu_halt.getOrElse(false.B)
+          Cat(slices.zipWithIndex.map { case (s, i) => s.io.l2FlushDone.getOrElse(false.B)}).andR && io_cpu_wfi.getOrElse(false.B)
         }
 
         /**