Microtage merage (#775)

* cpu-o3: split microtage out of tage

* cpu-o3: enhance branch index calculation in MicroTAGE to handle edge cases

* cpu-o3: update blockWidth calculation to handle zero blockSize

Change-Id: I44b6175022a3a593ed385407bd95ec0c40c74642

* cpu-o3: adjust MicroTAGE parameters and clean up code for clarity

Change-Id: I16ce79a7d8488d9a138d0a26f5500576ae54132e

* cpu-o3: remove unused variable 'usingBasetable'

Change-Id: I8be037a1cdacd7151f4fe8e743a32cca90a85036

* cpu-o3: MicroTAGE to remove base table and alternative prediction

Change-Id: I6b9c92c18c574a12c19532ae0b894e64c1187342

* cpu-o3: update MicroTAGE parameters for consistency

Change-Id: I953965b8e6feb1c15a238ac832d65bc16b32f496

* cpu-o3: remove alternative prediction logic

Change-Id: I39cd471d452aa343c3dd741a80fdfa7d126e3a9f

* cpu-o3: refine MicroTAGE parameters and remove unused variables

Change-Id: I3567ae93652aac218c5b4646003abadddaf7cf32

* cpu-o3: update MicroTAGE history length parameter to 16

Change-Id: If7c9d3aa68a23c36dde74d8cf3a286c9c48f3e3c

* cpu-o3: enhance MicroTAGE history management with ahead queues

Change-Id: I83277ae5c801e9d22b594286580459d12cdec69b

* cpu-o3:open microtage

Change-Id: I394246af184d3f07e02b85f06e4e5ceed368ec22

* cpu-o3:close utage in ideal

Change-Id: I762c11f8d15262fb9f1c9d443f77895fa76bbc79

* cpu-o3: update folded history queue size limit

Change-Id: Ia9bcdc028235447e254889d95e5ea98e7f067664

* cpu-o3: disable MicroTAGE in branch prediction configuration

Change-Id: I56614e8ebc2dd33320d353562087ab456fc452da

* cpu-o3: refine folded history queue management in doUpdateHist

Change-Id: Icdc7ac7f047a36dba6733a0e1d11e5e37aa4cdf1

* cpu-o3: update .gitignore and modify MicroTAGE predictor includes

Change-Id: I9cb7e7ef04efefbcbdbf705563563f50f3c83324

* cpu-o3: refactor MicroTAGE history management by removing ahead index history queue

* cpu-o3: disable MicroTAGE predictor in setKmhV3Ideal

Change-Id: Iad486579b9ab0df207013348f02c6be30bd10cfd

* cpu-o3: enhance MicroTAGE predictor to support alternative tag history

* cpu-o3:enable utage in idael

Change-Id: I20e9fbfe161cd741b37bb69d46e99ee7755f79e5

* cpu-o3: remove alternative tag history from MicroTAGE index

Change-Id: If1187310e575a7c485d49fb89215742b1174393a

* cpu-o3: implement ahead index history management in MicroTAGE

Change-Id: I2b9f9216a54405d517538958b717a8e3de2eca8a

* cpu-o3: add debug logging in MicroTAGE updates

Change-Id: I8c70b06b834fd5e713ef9ac4d3b26ec5b01ce2e6

* cpu-o3: update index folded history recovery in MicroTAGE

Change-Id: Ic736ea7cc73abebb3af473510c16d837b4f535f4

* cpu-o3: update doUpdateHist to handle ahead index folded history

Change-Id: I94ccc54b623bbf488bdaae9086c3cfff92c1fcdf

* cpu-o3: enhance ahead index history management in MicroTAGE

Change-Id: Ic7a506f9ee3bbbcaaf6b50f28cf74dc4a407cea8

* cpu: Add UTAGE flag and clean up MicroTAGE

Change-Id: Iffd21dbdb9f633841d1a9ac33dcd4e7f5f53b992

* cpu-o3: correct invalidation logic for duplicated entries in AheadBTB

* cpu-o3: update uTAGE parameters *4 for improved configuration

Change-Id: I93ab507fc32d1096a5fd07f68d85740577eb6ea9

* cpu-o3: fix invalidation logic for duplicated entries in AheadBTB

Change-Id: I72fbca71841e9209f8803e928af907a8c1106bf2

* cpu-o3: refine MicroTAGE parameters for improved configuration

Change-Id: If64a72e75eb5e8ee4c280a8362577617efa0c964

* cpu-o3: update MicroTAGE parameters for improved configuration

Change-Id: I0b5a16c19b91c36649a17171e49eb000626e7b98

* cpu-o3: update MicroTAGE history lengths for improved accuracy

Change-Id: I32ce96420169227820174c54ea4d7b423b910d22

* cpu-o3: tune MicroTAGE params and fix folded hist check

Change-Id: I67953b502b3d2cb0f08a66f58537f6eaa800cdf1

* cpu-o3: Tune uTAGE defaults and ignore spec06 outputs

Change-Id: Ic0faea91ca80f67e9b106eab459e3098bfe3b5a9

* util: Revert spec06 ignore pattern

Change-Id: I34219f5fc8b3c4ac7ed515dd57aaca6543fcb4ba

* cpu-o3: Remove unused includes

Change-Id: I727d76e59df69d0cef0089b87a4e671ca25546b9

* cpu-o3: Use FetchTarget in MicroTAGE interfaces

Change-Id: I15c1f248fa079ddd5b8cf4525fbaf23e04ddb1cf

---------

Co-authored-by: Cao Jiaming <caojiaming@bosc.ac.cn>

Author: CJ362ff

configs/example/idealkmhv3.py

@@ -85,6 +85,7 @@ def setKmhV3IdealParams(args, system):
         if args.bp_type == 'DecoupledBPUWithBTB':
             cpu.branchPred.ftq_size = 64
             cpu.branchPred.fsq_size = 64
+            # cpu.branchPred.microtage.enabled = False
 
         # l1 cache per core
         if args.caches:

configs/example/kmhv3.py

@@ -101,7 +101,7 @@ def setKmhV3Params(args, system):
 
             cpu.branchPred.ubtb.enabled = True
             cpu.branchPred.abtb.enabled = True
-            cpu.branchPred.microtage.enabled = False
+            cpu.branchPred.microtage.enabled = True
             cpu.branchPred.mbtb.enabled = True
             cpu.branchPred.tage.enabled = True
             cpu.branchPred.ittage.enabled = True

src/cpu/pred/BranchPredictor.py

@@ -1060,16 +1060,33 @@ class BTBTAGE(TimedBaseBTBPredictor):
     enableBankConflict = Param.Bool(False, "Enable bank conflict simulation")
     numDelay = 2
 
-class MicroTAGE(BTBTAGE):
-    """A smaller TAGE predictor configuration to assist uBTB"""
-    enableSC = Param.Bool(False, "Enable SC or not")    # TODO: BTBTAGE doesn't support SC
-    numPredictors = 1
-    tableSizes = [512]
-    TTagBitSizes = [16]
-    TTagPcShifts = [1]
+class MicroTAGE(TimedBaseBTBPredictor):
+    """Micro-sized BTB TAGE predictor used alongside uBTB"""
+    type = 'MicroTAGE'
+    cxx_class = 'gem5::branch_prediction::btb_pred::MicroTAGE'
+    cxx_header = "cpu/pred/btb/microtage.hh"
+
+    needMoreHistories = Param.Bool(True, "MicroTAGE needs more histories")
+    enableSC = Param.Bool(False, "Enable SC or not")
+    updateOnRead = Param.Bool(True,"Enable update on read, no need to save tage meta in FTQ")
+    # Keep vector parameters consistent with numPredictors to avoid constructor asserts.
+    numPredictors = Param.Unsigned(4, "Number of TAGE predictors")
+    tableSizes = VectorParam.Unsigned([512] * 4,"the TAGE T0~Tn length")
+    TTagBitSizes = VectorParam.Unsigned([16] * 4 ,"the T0~Tn entry's tag bit size")
+    TTagPcShifts = VectorParam.Unsigned([1] * 4 ,"when the T0~Tn entry's tag generating, PC right shift")
+    blockSize = Param.Unsigned(32,"tage index function uses 32B aligned block address")
 
-    histLengths = [16]
-    numDelay = 0
+    histLengths = VectorParam.Unsigned([5,9,17,27] ,"the BTB TAGE T0~Tn history length")
+    maxHistLen = Param.Unsigned(970,"The length of history passed from DBP")
+    numTablesToAlloc = Param.Unsigned(1,"The number of table to allocated each time")
+    numWays = Param.Unsigned(1, "Number of ways per set")
+    baseTableSize = Param.Unsigned(256,"Base table size")
+    maxBranchPositions = Param.Unsigned(32,"Maximum branch positions per 64-byte block")
+    useAltOnNaSize = Param.Unsigned(128,"Size of the useAltOnNa table")
+    useAltOnNaWidth = Param.Unsigned(7,"Width of the useAltOnNa table")
+    numBanks = Param.Unsigned(4,"Number of banks for bank conflict simulation")
+    enableBankConflict = Param.Bool(False,"Enable bank conflict simulation")
+    numDelay = Param.Unsigned(0,"Prediction latency in cycles")
 
 class BTBITTAGE(TimedBaseBTBPredictor):
     type = 'BTBITTAGE'
@@ -1170,7 +1187,7 @@ class DecoupledBPUWithBTB(BranchPredictor):
     numStages = Param.Unsigned(4, "Maximum number of stages in the pipeline")
     ubtb = Param.UBTB(UBTB(), "UBTB predictor")
     abtb = Param.AheadBTB(AheadBTB(), "ABTB predictor")
-    microtage = Param.BTBTAGE(MicroTAGE(), "MicroTAGE predictor to assist uBTB")
+    microtage = Param.MicroTAGE(MicroTAGE(), "MicroTAGE predictor to assist uBTB")
     mbtb = Param.MBTB(MBTB(), "MBTB predictor")
     tage = Param.BTBTAGE(BTBTAGE(), "TAGE predictor")
     ittage = Param.BTBITTAGE(BTBITTAGE(), "ITTAGE predictor")

src/cpu/pred/SConscript

@@ -49,7 +49,8 @@ SimObject('BranchPredictor.py', sim_objects=[
     'DecoupledStreamBPU', 'DefaultFTB', 'DecoupledBPUWithFTB',
     'TimedBaseFTBPredictor', 'FTBTAGE', 'FTBRAS', 'FTBuRAS', 'FTBITTAGE',
     'AheadBTB', 'MBTB', 'UBTB', 'DecoupledBPUWithBTB',
-    'TimedBaseBTBPredictor', 'BTBRAS', 'BTBTAGE', 'BTBITTAGE', 'BTBMGSC'], enums=["BpType"])
+    'TimedBaseBTBPredictor', 'BTBRAS', 'BTBTAGE', 'MicroTAGE',
+    'BTBITTAGE', 'BTBMGSC'], enums=["BpType"])
 
 DebugFlag('Indirect')
 Source('bpred_unit.cc')
@@ -100,6 +101,7 @@ Source('btb/abtb.cc')
 Source('btb/mbtb.cc')
 Source('btb/timed_base_pred.cc')
 Source('btb/btb_tage.cc')
+Source('btb/microtage.cc')
 Source('btb/btb_ittage.cc')
 Source('btb/btb_mgsc.cc')
 Source('btb/folded_hist.cc')
@@ -125,6 +127,7 @@ DebugFlag('FTB')
 DebugFlag('TAGE')
 DebugFlag('TAGEUseful')
 DebugFlag('TAGEHistory')
+DebugFlag('UTAGE')
 DebugFlag('ITTAGE')
 DebugFlag('ITTAGEHistory')
 DebugFlag('FoldedHist')

src/cpu/pred/btb/decoupled_bpred.hh

@@ -20,6 +20,7 @@
 #include "cpu/pred/btb/btb_tage.hh"
 #include "cpu/pred/btb/btb_ubtb.hh"
 #include "cpu/pred/btb/mbtb.hh"
+#include "cpu/pred/btb/microtage.hh"
 #include "cpu/pred/btb/ras.hh"
 #include "cpu/pred/general_arch_db.hh"
 
@@ -81,7 +82,7 @@ class DecoupledBPUWithBTB : public BPredUnit
     UBTB *ubtb{};
     AheadBTB *abtb{};
     MBTB *mbtb{};
-    BTBTAGE *microtage{};
+    MicroTAGE *microtage{};
     BTBTAGE *tage{};
     BTBITTAGE *ittage{};
     BTBMGSC *mgsc{};