mem: fix ddr 100delay

edwu186 · edwu186 · commit 5ba1af302d20 · 2026-01-15T16:45:05.000+08:00
Change-Id: I697b252773fd7a19e62b856975721b1daabf54af
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
@@ -213,7 +213,7 @@ class L3ToMemBus(CoherentXBar):
     # contributions.
     frontend_latency = 0
     forward_latency = 9
-    response_latency = 191
+    response_latency = 224
     snoop_response_latency = 4
 
     # Use a snoop-filter by default
