configs,arch-riscv,cpu-o3: Fix Xiangshan raw Linux boot (#778)

* configs,arch-riscv,cpu-o3: Fix Xiangshan raw Linux boot

Restore the raw linux.bin bringup path used by kmhv3.py.

Inject a Xiangshan DTB for raw checkpoints, pass its address through A1,
and make sfence.vma wait for older stores before committing so Linux can
finish early page-table setup and boot to userspace again.

Change-Id: Ie0c5105ff20df242bb37b29ae0fcae75332ce087

* tests,configs: Add Xiangshan raw Linux boot CI

Add a post-merge workflow job that boots the shared raw linux.bin
image with kmhv3.py and checks for the expected XiangShan banner and
m5_exit completion signal.

The job uses XS_LINUX_BIN when provided and otherwise falls back to the
shared /nfs/home/share/gem5_ci/ready-to-run/linux.bin path on the CI
runners.

Change-Id: I816b141e97a74fa09fdb59796e048df666e70882

* tests: Increase CI from 10 to 30 minutes to avoid canceled

Change-Id: If8a90c04b21512599457e5581ed7e8248f9b7117

* tests: only test boot linux CI

Change-Id: I8b5c34bad49b70eb49b71273a6ef6ae58dd9eae2

* tests: fix boot linux CI

Change-Id: I3e2ee9f179faed7d15668c7018b06688c200d36a

* arch-riscv, configs: Fix Sv48 difftest Linux boot

Change-Id: If6e579d718eb6d67e18528a00eacdec31fccc393

* Revert "tests: only test boot linux CI"

This reverts commit 051f8de.

Author: jensen-yan

.github/workflows/gem5.yml

@@ -142,3 +142,35 @@ jobs:
           cd $GEM5_HOME/util/xs_scripts/test_h
           bash ../kmh_6wide_h.sh /nfs/home/share/gem5_ci/checkpoints/gcbh_test.zstd
 
+  raw_linux_boot_test:
+    runs-on: [self-hosted, open]
+    continue-on-error: false
+    timeout-minutes: 30
+    name: XS-GEM5 - Boot raw Linux
+    steps:
+      - uses: actions/checkout@v2
+      - uses: ./.github/actions/build-dramsim
+      - name: Build GEM5 opt
+        run: |
+          CC=gcc CXX=g++ scons build/RISCV/gem5.opt --linker=gold -j64
+      - name: Boot Xiangshan raw Linux
+        run: |
+          export RAW_LINUX_BIN="${XS_LINUX_BIN:-/nfs/home/share/gem5_ci/ready-to-run/linux.bin}"
+          if [ ! -r "$RAW_LINUX_BIN" ]; then
+            echo "Missing raw linux image: $RAW_LINUX_BIN"
+            echo "Please provision the image at the default path or set XS_LINUX_BIN on the runner."
+            exit 1
+          fi
+
+          mkdir -p debug/raw_linux_ci
+          ./build/RISCV/gem5.opt -r -d debug/raw_linux_ci \
+            ./configs/example/kmhv3.py \
+            --raw-cpt \
+            --generic-rv-cpt "$RAW_LINUX_BIN" \
+            --disable-difftest
+      - name: Check boot result
+        run: |
+          test -f debug/raw_linux_ci/simout
+          tail -n 200 debug/raw_linux_ci/simout
+          grep -q "Hello, XiangShan!" debug/raw_linux_ci/simout
+          grep -q "m5_exit instruction encountered" debug/raw_linux_ci/simout

configs/common/FSConfig.py

@@ -658,14 +658,20 @@ def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None):
     return self
 
 def makeBareMetalXiangshanSystem(mem_mode, mdesc=None, cmdline=None, np=1, ruby=False):
+    self = makeXiangshanPlatformSystem(mem_mode, mdesc, np=np, ruby=ruby)
+    self.workload = RiscvBareMetal()
+    self.workload.reset_vect = 0x80000000
+    return self
+
+
+def makeXiangshanPlatformSystem(mem_mode, mdesc=None, np=1, ruby=False):
     self = System()
     if not mdesc:
         # generic system
         mdesc = SysConfig()
     self.mem_mode = mem_mode
     self.mem_ranges = [AddrRange(start=0x80000000, size=mdesc.mem())]
     print(self.mem_ranges)
-    self.workload = RiscvBareMetal()
 
     self.iobus = IOXBar()
     if not ruby:
@@ -698,7 +704,6 @@ def makeBareMetalXiangshanSystem(mem_mode, mdesc=None, cmdline=None, np=1, ruby=
             AddrRange(self.plic.pio_addr, self.plic.pio_addr + self.plic.pio_size),
             ]
 
-    self.workload.reset_vect = 0x80000000
     if not ruby:
         self.system_port = self.membus.cpu_side_ports
     return self

configs/common/Options.py

@@ -632,38 +632,47 @@ def addFSOptions(parser):
     parser.add_argument("--wait-gdb", default=False, action='store_true',
                         help="Wait for remote GDB to connect.")
 
-def addXiangshanFSOptions(parser):
+def addXiangshanCommonOptions(parser):
     # Xiangshan related options
-    parser.add_argument("--xiangshan-system", action= "store_true",
+    parser.add_argument("--xiangshan-system", action="store_true",
                         help="Use memory layout of Xiangshan system")
-
-    parser.add_argument("--enable-h-gcpt", action= "store_true",
-                        help="enable h checkpoint")
-    parser.add_argument("--generic-rv-cpt", action= "store", type = str,
-                        default=None, required=True,
-                        help="The path of Xiangshan risc-v checkpoint")
-    parser.add_argument("--gcpt-restorer", action="store", type = str,
-                      default=None,
-                      help="The path of generic risc-v checkpoint restorer")
-
-    parser.add_argument("--raw-cpt", action= "store_true",
-                        help = "The checkpoint file is not gz but binary")
-
     parser.add_argument("--mmc-img", action="store", type=str,
                         default=None, help="The path of mmc img")
     parser.add_argument("--mmc-cptbin", action="store",
                         type=str, default=None, help="The path of mmc cptbin")
 
     # Difftest option
+    parser.set_defaults(enable_difftest=None)
     parser.add_argument("--enable-difftest",
                         action="store_true",
+                        dest="enable_difftest",
                         help="use NEMU as ref to do difftest")
+    parser.add_argument("--disable-difftest",
+                        action="store_false",
+                        dest="enable_difftest",
+                        help="disable NEMU difftest")
 
     parser.add_argument("--difftest-ref-so",
                         action="store",
                         default=None,
                         help="The shared lib file used to do difftest")
 
+
+def addXiangshanFSOptions(parser):
+    addXiangshanCommonOptions(parser)
+
+    parser.add_argument("--enable-h-gcpt", action= "store_true",
+                        help="enable h checkpoint")
+    parser.add_argument("--generic-rv-cpt", action= "store", type = str,
+                        default=None, required=True,
+                        help="The path of Xiangshan risc-v checkpoint")
+    parser.add_argument("--gcpt-restorer", action="store", type = str,
+                      default=None,
+                      help="The path of generic risc-v checkpoint restorer")
+
+    parser.add_argument("--raw-cpt", action= "store_true",
+                        help = "The checkpoint file is not gz but binary")
+
 def addXiangshanTraceOptions(parser):
     # Add trace-specific arguments for trace-driven simulation
     parser.add_argument('--enable-trace-mode', action='store_true',